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參數(shù)資料
| 型號(hào)： | Eval-AD1940EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | SigmaDSP-TM Multichannel 28-Bit Audio Processor |
| 中文描述： | SigmaDSP的，商標(biāo)多通道28位音頻處理器 |
| 文件頁數(shù)： | 11/32頁 |
| 文件大?。?/td> | 478K |
| 代理商： | EVAL-AD1940EB |
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AD1940
PIN FUNCTIONS
Table 10 shows the AD1940’s pin numbers, names, and
functions. Input pins have a logic threshold compatible with
TTL input levels and may be used in systems with 3.3 V or
5 V logic.
SDATA_IN0
SDATA_IN1
SDATA_IN2/TDM_IN1
SDATA_IN3/TDM_IN0
Serial Data/TDM Inputs. The serial format is selected by writing
to Bits 2:0 of the serial input port control register. SDATA_IN2
and SDATA_IN3 are dual-function pins that can be set to a
variety of standard 2-channel formats or to TDM mode. Two of
these four pins (SDATA_IN2 and SDATA_IN3) can be used as
TDM inputs in either dual-wire 8-channel mode or single-wire
16-channel mode (TDM_O0 only). In dual-wire 8-channel
mode, Channels 0-7 will be input on SDATA_IN3 and
Channels 8-15 on SDATA_IN2. In single-wire 16-channel
mode, Channels 0-15 will be input on SDATA_IN2. See the
Serial Data Input/Output Ports section for further explanation.
LRCLK_IN
BCLK_IN
Left/Right and Bit Clocks for Timing the Input Data. These
input clocks are associated with the SDATA_IN0-3 signals. The
input port is always in a slave configuration. These pins also
function as frame sync and bit clock for the input TDM stream.
SDATA_OUT0/TDM_O0
SDATA_OUT1
SDATA_OUT2,
SDATA_OUT3
SDATA_OUT4/TDM_O1
SDATA_OUT5
SDATA_OUT6
SDATA_OUT7/DCSOUT
Serial Data/TDM/Data Capture Outputs. These pins are used
for serial digital outputs. For non-TDM systems, these eight
pins can output 16 channels of digital audio, using a variety of
standard two-channel formats. They are grouped into two
groups of four pins (0-3 and 4-7); each group can be indepen-
dently set to any of the available serial modes, allowing the
AD1940 to simultaneously communicate with two external
devices with different serial formats. Two of these eight pins
(SDATA_OUT0 and SDATA_OUT4) can be used as TDM
outputs in either dual-wire 8-channel mode or single-wire
16-channel mode (TDM_OUT0 only). In dual-wire 8-channel
mode, Channels 0-7 will be output on SDATA_OUT0 and
Channels 8-15 on SDATA_OUT4. See the Serial Data
Input/Output Ports section for further explanation.
SDATA_OUT7 can also be used as a data capture output, as
described in the Data Capture Registers section.
Rev. 0 | Page 11 of 32
LRCLK_OUT0
BCLK_OUT0
Output Clocks. This clock pair is used for outputs
SDATA_OUT0–3. In slave mode, these clocks are inputs
to the AD1940. On power-up, these pins are set to slave
mode to avoid conflicts with external master-mode devices.
LRCLK_OUT1
BCLK_OUT1
Output Clocks. This clock pair is used for outputs
SDATA_OUT4–7. In slave mode, these clocks are inputs
to the AD1940. On power-up, these pins are set to slave
mode to avoid conflicts with external master-mode devices.
MCLK
Master Clock Input. The AD1940 uses a PLL to generate the
appropriate internal clock for the DSP core. An in-depth
description of using the PLL is found in the Setting Master
Clock/PLL Mode section.
PLL_CTRL0
PLL_CTRL1
PLL_CTRL2
PLL Mode Control Pins. The functionality of these pins is
described in the Setting Master Clock/PLL Mode section.
CDATA
Serial Data Input for the SPI Control Port.
COUT
Serial Data Output for the SPI Port. This is used for reading
back registers and memory locations. It is three-stated when an
SPI read is not active.
CCLK
SPI Bit Clock. This clock may either run continuously or be
gated off in between SPI transactions.
CLATCH
SPI Latch Signal. This must go low at the beginning of an SPI
transaction and high at the end of a transaction. Each SPI
transaction may take a different number of CCLKs to complete,
depending on the address and read/write bit that are sent at the
beginning of the SPI transaction.
ADR_SEL
Address Select. This pin selects the address for the AD1940’s
communication with the control port. This allows two AD1940s
to be used with a single CLATCH signal.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD1940MINIB | 制造商:Analog Devices 功能描述:SIGMADSP EVAL BD - Bulk 制造商:Rochester Electronics LLC 功能描述: |
| EVAL-AD1940MINIBZ | 功能描述:BOARD EVAL AD1940 MINI SIGMADSP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| EVAL-AD1941EB | 制造商:Analog Devices 功能描述:EVAL BD SIGMADSPMULTICHANAUDIO PROCESSOR - Bulk |
| EVAL-AD1953EB | 制造商:Analog Devices 功能描述:EVAL BRD FOR 3 CH 24 BIT SIG-PROCESS DAC - Bulk 制造商:Analog Devices 功能描述:EVALUATION KIT ((NS)) |
| EVAL-AD1953EBZ | 制造商:Analog Devices 功能描述:EVAL BRD FOR 3 CH 24 BIT SIG-PROCESS DAC - Bulk |
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