參數(shù)資料
型號(hào)： Eval-AD1940EB
廠商： Analog Devices, Inc.
英文描述： SigmaDSP-TM Multichannel 28-Bit Audio Processor
中文描述： SigmaDSP的，商標(biāo)多通道28位音頻處理器
文件頁(yè)數(shù)： 20/32頁(yè)
文件大?。?/td> 478K
代理商： EVAL-AD1940EB
AD1940
Table 17. Data Capture Control Registers (2634–2641)
Register Bits
Function
12:2
11-Bit Program Counter Address
1:0
Register Select
00 = Mult_X_input
01 = Mult_Y_input
10 = MAC_output
11 = Accum_fback
DATA CAPTURE REGISTERS
The AD1940’s data capture feature allows the data at any node
in the signal processing flow to be sent to one of six control
port-readable registers or to a serial output pin. This can be
used to monitor and display information about internal signal
levels or compressor/limiter activity.
Rev. 0 | Page 20 of 32
The AD1940 contains six independent control port-readable
data capture registers, and two digital output capture registers.
The digital output registers are output on SDATA_OUT7 when
the data capture serial out enable bit (Bit 14) is set in Serial
Output Control Register 2. These registers are useful when
debugging the signal processing flow.
For each of the data capture registers, a capture count and a
register select must be set. The capture count is a number
between 0 and 1,535 that corresponds to the program step
number where the capture will occur. The register select field
programs one of four registers in the DSP core that will be
transferred to the data capture register when the program
counter equals the capture count. The register select field
selections are shown in Table 18.
Table 18. Data Capture Output Register Select
Setting
Register
00
Multiplier X Input (Mult_X_input)
01
Multiplier Y Input (Mult_Y_input)
10
Multiplier-Accumulator Output
(MAC_out)
11
Accumulator Feedback (Accum_fback)
The capture count and register select bits are set by writing to
one of the eight data capture registers at register addresses
2634: Control Port Data Capture Setup Register 0
2635: Control Port Data Capture Setup Register 1
2636: Control Port Data Capture Setup Register 2
2637: Control Port Data Capture Setup Register 3
2638: Control Port Data Capture Setup Register 4
2639: Control Port Data Capture Setup Register 5
2640: Digital Out Data Capture Setup Register 0
2641: Digital Out Data Capture Setup Register 1
The captured data is in 5.19 twos complement data format for
all eight register select fields. The four LSBs are truncated from
the internal 5.23 data-word.
The data that must be written to set up the data capture is a
concatenation of the 11-bit program count index with the 2-bit
register select field. The capture count and register select values
that correspond to the desired point to be monitored in the
signal processing flow can be found in a file output from the
program compiler. The capture registers can be accessed by
reading from locations 2634 to 2639 (for control port capture
registers). The format for reading and writing to the data
capture registers can be seen in Table 27 and Table 28.
Table 19. DSP Core Control Register (2642)
Register Bits
Function
15:14
Reserved
13
Slew RAM Muted (Read Only)
12
Mute Slew RAM, All Locations
11
Reserved, Set to 0
10
Use Serial Out LRCLK for Output Latch
9
Clear Internal Registers to All 0s, Active Low
8
Force Multiplier to 0
7
Inititalize Data Memory with 0s
6
Mute Serial Input Port
5
Initiate Safe Transfer to Target RAM
4
Initiate Safe Transfer to Parameter RAM
3:2
Input Serial Port to Sequencer Sync
00 = LRCLK
01 = LRCLK/2
10 = LRCLK/4
11 = LRCLK/8
1:0
Program Length
00 = 1536
01 = 768
10 = 384
11 = 192
DSP CORE CONTROL REGISTER
The controls in this register set the operation of the AD1940’s
DSP core. Bits 6 to 9 can be set to initiate a shutdown of the
core. The output is muted when this is performed, so it is best to
first assert the mute slew RAM bit (if slew RAM locations are
used as volume controls in the program) to avoid a click or pop
when shutdown is asserted.
Slew RAM Muted (Bit 13)
This bit is set to 1 when the slew RAM mute operation has been
completed. This bit is read-only and is automatically cleared by
reading.
Mute Slew RAM, All Locations (Bit 12)
Setting this bit to 1 initiates a mute of all 64 slew RAM
locations. When reset to 0, all RAM locations return to their
previous state. This bit is only functional if slew RAM locations
are used in the custom program design. Keep in mind that the
AD1940’s default program does not use any slew RAM volume
controls, so this bit has no effect in that case. The mute
operation is identical to writing all 0s to the data portion of the
target RAM, and therefore the time constant and linear/
exponential curve selection is determined by the bits that have
相關(guān)PDF資料
PDF描述
EVAL-AD1953EB 16-bit fixed point DSP with Flash
EVAL-AD1958EB PLL/Multibit DAC
EVAL-AD1959EB PLL/Multibit DAC
EVAL-AD1974EB 4 ADC with PLL, 192 kHz, 24-Bit Codec
EVAl-AD1974EBZ 4 ADC with PLL, 192 kHz, 24-Bit Codec
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-AD1940MINIB 制造商:Analog Devices 功能描述:SIGMADSP EVAL BD - Bulk 制造商:Rochester Electronics LLC 功能描述:
EVAL-AD1940MINIBZ 功能描述:BOARD EVAL AD1940 MINI SIGMADSP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
EVAL-AD1941EB 制造商:Analog Devices 功能描述:EVAL BD SIGMADSPMULTICHANAUDIO PROCESSOR - Bulk
EVAL-AD1953EB 制造商:Analog Devices 功能描述:EVAL BRD FOR 3 CH 24 BIT SIG-PROCESS DAC - Bulk 制造商:Analog Devices 功能描述:EVALUATION KIT ((NS))
EVAL-AD1953EBZ 制造商:Analog Devices 功能描述:EVAL BRD FOR 3 CH 24 BIT SIG-PROCESS DAC - Bulk
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*