- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362799 > Eval-AD1940EB (Analog Devices, Inc.) SigmaDSP-TM Multichannel 28-Bit Audio Processor PDF資料下載
參數(shù)資料
| 型號： | Eval-AD1940EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | SigmaDSP-TM Multichannel 28-Bit Audio Processor |
| 中文描述： | SigmaDSP的，商標(biāo)多通道28位音頻處理器 |
| 文件頁數(shù)： | 14/32頁 |
| 文件大?。?/td> | 478K |
| 代理商： | EVAL-AD1940EB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
AD1940
CONTROL PORT
OVERVIEW
The AD1940 has many different control options that can be set
through an SPI interface. Most signal processing parameters are
controlled by writing new values to the parameter RAM using
the control port. Other functions, such as mute and input/
output mode control, are programmed by writing to the
control registers.
Rev. 0 | Page 14 of 32
The control port is capable of full read/write operation for all of
the memories and registers. All addresses may be accessed in
both a single-address mode or a burst mode. A control word
consists of the chip address, the register/RAM subaddress, and
the data to be written. The data can be variable in its byte width.
The first byte of a control word (Byte 0) contains the 7-bit chip
address plus the R/W bit. The next two bytes (Bytes 1 and 2)
together form the subaddress of the memory or register
location within the AD1940. This subaddress needs to be two
bytes because the memories within the AD1940 are directly
addressable, and their sizes exceed the range of single-byte
addressing. All subsequent bytes (Bytes 3, 4, etc.) contain the
data, such as control port data or program or parameter data.
The AD1940 has several mechanisms for updating signal
processing parameters in real time without causing pops or
clicks. In cases where large blocks of data need to be down-
loaded, the output of the DSP core can be halted (using Bit 9 of
the core control register), new data loaded, and then restarted.
This is typically done during the booting sequence at start-up or
when loading a new program into RAM. In cases where only a
few parameters need to be changed, they can be loaded without
halting the program. To avoid unwanted side effects while
loading parameters on the fly, the SigmaDSP provides the
safeload registers. The safeload registers can be used to buffer a
full set of parameters (e.g. the five coefficients of a biquad) and
then transfer these parameters into the active program within
one audio frame. The safeload mode uses internal logic to
prevent contention between the DSP core and the control port.
The SPI port uses a 4-wire interface, consisting of CLATCH,
CCLK, CDATA, and COUT signals. The CLATCH signal goes
low at the beginning of a transaction and high at the end of a
transaction. The CCLK signal latches CDATA on a low-to-high
transition. COUT data is shifted out of the AD1940 on the
falling edge of CCLK and should be clocked into the receiving
device, such as a microcontroller, on CCLK’s rising edge. The
CDATA signal carries the serial input data, and the COUT
signal is the serial output data. The COUT signal remains three-
stated until a read operation is requested. This allows other SPI-
compatible peripherals to share the same readback line. All SPI
transactions follow the same basic format, shown in Table 11. A
timing diagram is shown in Figure 4. All data written should be
MSB-first.
Table 11. Generic SPI Word Format
Byte 0
chip_adr [6:0],
R/W
Byte 1
0000,
adr[11:8]
Byte 2
Byte 3
Byte 4,
etc.
adr[7:0] data
data
Chip Address R/W
The first byte of an SPI transaction includes the 7-bit chip
address and a R/W bit. The chip address is set by the ADR_SEL
pin. This allows two AD1940s to share a CLATCH signal, yet
still operate independently. When ADR_SEL is low, the chip
address is 0000000; when it is high, the address is 0000001. The
LSB of this first byte determines whether the SPI transaction is
a read (Logic Level 1) or a write (Logic Level 0).
RAM/Register Address
The 12-bit RAM/register address word is decoded into a
location in one of the memories or registers.
Data Bytes
The number of data bytes varies according to the register or
memory being accessed. In burst write mode, an initial address
is given followed by a continuous sequence of data for
consecutive memory/register locations. The detailed data
format diagram for continuous-mode operation is given in the
Control Port Read/Write Data Formats section.
A sample timing diagram for a single SPI write operation to the
parameter RAM is shown in Figure 9. A sample timing diagram
of a single SPI read operation is shown in Figure 10. The COUT
pin goes from three-state to driven at the beginning of Byte 3.
In this example, Bytes 0 to 2 contain the addresses and R/W bit,
and subsequent bytes carry the data. The exact formats for
specific types of writes are shown in Table 21 to Table 30.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EVAL-AD1953EB | 16-bit fixed point DSP with Flash |
| EVAL-AD1958EB | PLL/Multibit DAC |
| EVAL-AD1959EB | PLL/Multibit DAC |
| EVAL-AD1974EB | 4 ADC with PLL, 192 kHz, 24-Bit Codec |
| EVAl-AD1974EBZ | 4 ADC with PLL, 192 kHz, 24-Bit Codec |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD1940MINIB | 制造商:Analog Devices 功能描述:SIGMADSP EVAL BD - Bulk 制造商:Rochester Electronics LLC 功能描述: |
| EVAL-AD1940MINIBZ | 功能描述:BOARD EVAL AD1940 MINI SIGMADSP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| EVAL-AD1941EB | 制造商:Analog Devices 功能描述:EVAL BD SIGMADSPMULTICHANAUDIO PROCESSOR - Bulk |
| EVAL-AD1953EB | 制造商:Analog Devices 功能描述:EVAL BRD FOR 3 CH 24 BIT SIG-PROCESS DAC - Bulk 制造商:Analog Devices 功能描述:EVALUATION KIT ((NS)) |
| EVAL-AD1953EBZ | 制造商:Analog Devices 功能描述:EVAL BRD FOR 3 CH 24 BIT SIG-PROCESS DAC - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。