
AD1940
RAMS AND REGISTERS
Table 12. Control Port Addresses
SPI Address
0–1023 (0x0000–0x03FF)
1024–2559 (0x0400–0x09FF)
2560–2623 (0x0A00–0x0A3F)
2624–2628 (0x0A40–0x0A44)
2629–2633 (0x0A45–0x0A49)
2634–2639 (0x0A4A–0x0A4F)
2640–2641 (0x0A50–0x0A51)
2642 (0x0A52)
2643 (0x0A53)
2644 (0x0A54)
2645 (0x0A55)
2646 (0x0A56)
Table 13. RAM Read/Write Modes
Rev. 0 | Page 16 of 32
Register Name
Parameter RAM
Program RAM
Target/Slew RAM
Parameter RAM Data Safeload Registers 0–4
Parameter RAM Indirect Address Safeload Registers 0-4
Data Capture Registers 0–5 (Control Port Readback)
Data Capture Registers (Digital Output)
DSP Core Control Register
RAM Configuration Register
Serial Output Control Register 1 (Channels 0–7)
Serial Output Control Register 2 (Channels 8–15)
Serial Input Control Register
Read/Write Word Length
Write: 4 Bytes, Read: 4 Bytes
Write: 5 Bytes, Read: 5 Bytes
Write: 5 Bytes, Read: N/A
Write: 5 Bytes, Read: N/A
Write: 2 Bytes, Read: N/A
Write: 2 Bytes, Read: 3 Bytes
Write: 2 Bytes, Read: N/A
Write: 2 Bytes, Read: 2 Bytes
Write: 1 Byte, Read: 1 Byte
Write: 2 Bytes, Read: 2 Bytes
Write: 2 Bytes, Read: 2 Bytes
Write: 1 Byte, Read: 1 Byte
Memory
Parameter RAM
Size
1024 × 28
SPI Address
Range
0–1023
(0x0000–0x03FF)
1024–2559
(0x0400–0x09FF)
2560–2623
(0x0A00–0x0A3F)
Read
Yes
Write
Yes
Burst Mode
Available
Yes
Write Modes
Direct Write
1
Safeload Write
Program RAM
1536 × 40
Yes
Yes
Yes
Direct Write
1
Target/Slew RAM
64 × 34
No
Yes (via
Safeload)
Yes
2
Safeload Write
1
DSP core should be shut down first to avoid clicks/pops.
2
The target/slew RAMs need to be written through the safeload registers. Safeload writes may be done in either single-write or burst-mode.
CONTROL PORT ADDRESSING
Table 12 shows the addressing of the AD1940’s RAM and
register spaces. The address space encompasses a set of registers
and three RAMs: one each for holding signal processing
parameters, holding the program instructions, and ramping
parameter values. The program and parameter RAMs are
initialized on power-up from on-board boot ROMs.
Table 13 shows the sizes and available writing modes of the
parameter, program, and target/slew RAMs.
PARAMETER RAM CONTENTS
The parameter RAM is 28 bits wide and occupies Addresses 0 to
1023. The parameter RAM is initialized to all 0s on power-up.
The data format of the parameter RAM is twos complement
5.23. This means that the coefficients may range from +16.0
(minus 1 LSB) to –16.0, with 1.0 represented by the binary word
0000100000000000000000000000.
Options for Parameter Updates
The parameter RAM can be written and read using one of the
two following methods.
1.
Direct Read/Write
. This method allows direct access to the
program and parameter RAMs. This mode of operation is
normally used during a complete new load of the RAMs,
using burst-mode addressing. The clear registers bit in the
core control register should be set to 0 using this mode to
avoid any clicks or pops in the outputs. Note that it is also
possible to use this mode during live program execution,
but since there is no handshaking between the core and the
control port, the parameter RAM will be unavailable to the
DSP core during control writes, resulting in clicks and pops
in the audio stream.
2.
Safeload Writes.
Up to five safeload registers can be loaded
with address/data intended for the parameter RAM. The
data is then transferred to the requested address when the
RAM is not busy. This method can be used for dynamic
updates while live program material is playing through the
AD1940/AD1941. For example, a complete update of one
biquad section can occur in one audio frame, while the
RAM is not busy. This method is not available for writing
to the program RAM or control registers.
The following section discusses these two options in more
detail.