參數資料
型號: Eval-AD1940EB
廠商: Analog Devices, Inc.
英文描述: SigmaDSP-TM Multichannel 28-Bit Audio Processor
中文描述: SigmaDSP的,商標多通道28位音頻處理器
文件頁數: 12/32頁
文件大?。?/td> 478K
代理商: EVAL-AD1940EB
AD1940
RESETB
Active-Low Reset Signal. After RESETB goes high, the AD1940
goes through an initialization sequence where the program and
parameter RAMs are initialized with the contents of the on-
board boot ROMs. All registers are set to 0, and the data
RAMs are also set to 0. The initialization is complete after
8,192 internal MCLK cycles (referenced to the rising edge of
RESETB), which corresponds to 1,366 external MCLK cycles if
the part is in 256 × f
S
mode. New values should not be written to
the control port until the initialization is complete.
VREF
Voltage Reference for Regulator. This pin is driven by an
internal 1.15 V reference voltage.
VDRIVE
Drive for External Transistor. The base of the voltage regulator’s
external PNP transistor is driven from this pin.
VSENSE
Digital power level. The voltage level on the VDD pins is sensed
on VSENSE. VSENSE should be tied to VDD.
VSUPPLY
Main Supply Voltage Level. This pin is tied to the board’s main
voltage supply. This is usually 3.3 V or 5 V.
Rev. 0 | Page 12 of 32
VDD (4)
Digital VDD for Core. 2.5 V nominal.
GND (4)
Digital Ground.
PLL_VDD
Supply for AD1940 PLL. 2.5 V nominal.
PLL_GND
PLL Ground.
ODVDD (3)
VDD for All Digital Outputs. The high levels of the digital
output signals are set on this pin. The voltage can range from
2.5 V to 5.0 V.
INVDD
Peak Input Voltage Level. The highest voltage level that the
input pins will see should be connected to INVDD. This is to
protect the chip inputs from voltage overstress. The voltage on
this pin must always be at or above the level of ODVDD.
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