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型號(hào)：	EP1S30F780I6N
廠商：	Altera
文件頁(yè)數(shù)：	684/864頁(yè)
文件大?。?/td>	0K
描述：	IC STRATIX FPGA 30K LE 780-FBGA
產(chǎn)品培訓(xùn)模塊：	Three Reasons to Use FPGA's in Industrial Designs
產(chǎn)品變化通告：	Package Height Change 03/March/2008
標(biāo)準(zhǔn)包裝：	18
系列：	Stratix®
LAB/CLB數(shù)：	3247
邏輯元件/單元數(shù)：	32470
RAM 位總計(jì)：	3317184
輸入/輸出數(shù)：	597
電源電壓：	1.425 V ~ 1.575 V
安裝類型：	表面貼裝
工作溫度：	-40°C ~ 100°C
封裝/外殼：	780-BBGA
供應(yīng)商設(shè)備封裝：	780-FBGA（29x29）

Altera Corporation

Stratix Device Handbook, Volume 2

July 2005

Configuration

Above the standard I/O offered by APEX II, APEX 20K, and Stratix

devices, Stratix GX devices provide up to 20 3.175 Gbps transceivers. The

transceivers provide high-speed serial links for chip-to-chip, backplane,

and line-side connectivity and support a number of the emerging

high-speed protocols. You can find more information in the Stratix GX

Family Data Sheet in the Stratix GX Family Handbook, Volume 1.

Configuration

The Stratix and Stratix GX devices supports all current configuration

schemes, including the use of enhanced configuration devices, passive

serial (PS), passive parallel asynchronous (PPA), fast passive parallel

(FPP), and JTAG. Stratix and Stratix GX devices also provide a number of

new configuration enhancements that you can take advantage of when

migrating APEX II and APEX 20K designs to Stratix and Stratix GX

Configuration Speed & Schemes

You can configure Stratix and Stratix GX devices at a maximum clock

speed of 100 MHz, which is faster than the 66-MHz and 33-MHz

maximum configuration speeds for APEX II and APEX 20K devices,

respectively. Similar to APEX II devices, you can use 8-bit parallel data to

configure Stratix and Stratix GX devices (the target device can receive

byte-wide configuration data on each clock cycle) significantly speeding

up configuration times.

You can select a configuration scheme based on how the MSEL pins are

driven. Stratix and Stratix GX devices have three MSEL pins (APEX II and

APEX 20K devices have two MSEL pins) for determining the

configuration scheme.

registered_input

Specifies the clock source for the input synchronization registers,

which can be either tx_inclock or tx_coreclock. Used only

when the Registered Inputs option is selected.

common_rx_tx_pll

Indicates the fast PLL can be shared between receiver and transmitter

applications.

Notes to Tables 10–11 and 10–12:

You can specify these parameters in the MegaWizard Plug-In Manager.

You must specify a data rate in the MegaWizard Plug-In Manager instead of a W factor.

The same fast PLL can be used to clock both the receiver and transmitter only if both are running at the same

Table 10–12. New altlvds Parameters for Stratix LVDS Transmitter (Part 2 of 2) Note (1)

Parameter

Function

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