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型號(hào)：	EP1S30F780I6N
廠商：	Altera
文件頁(yè)數(shù)：	420/864頁(yè)
文件大?。?/td>	0K
描述：	IC STRATIX FPGA 30K LE 780-FBGA
產(chǎn)品培訓(xùn)模塊：	Three Reasons to Use FPGA's in Industrial Designs
產(chǎn)品變化通告：	Package Height Change 03/March/2008
標(biāo)準(zhǔn)包裝：	18
系列：	Stratix®
LAB/CLB數(shù)：	3247
邏輯元件/單元數(shù)：	32470
RAM 位總計(jì)：	3317184
輸入/輸出數(shù)：	597
電源電壓：	1.425 V ~ 1.575 V
安裝類(lèi)型：	表面貼裝
工作溫度：	-40°C ~ 100°C
封裝/外殼：	780-BBGA
供應(yīng)商設(shè)備封裝：	780-FBGA（29x29）

Altera Corporation

July 2005

Stratix Device Handbook, Volume 2

High-Speed Differential I/O Interfaces in Stratix Devices

The PCML I/O standard is a differential high-speed, low-power I/O

interface standard used in applications such as networking and

telecommunications. The standard requires a 3.3-V VCCIO. The PCML I/O

standard achieves better performance and consumes less power than the

LVPECL I/O standard. The PCML standard is similar to LVPECL, but

PCML has a reduced voltage swing, which allows for a faster switching

time and lower power consumption.See the Stratix Device Family Data

Sheet section of the Stratix Device Handbook, Volume 1 for the PCML

signaling characteristics.

Differential HSTL (Class I & II)

The differential HSTL I/O standard is used for applications designed to

operate in the 0.0- to 1.5-V HSTL logic switching range such as quad data

rate (QDR) memory clock interfaces. The differential HSTL specification

is the same as the single ended HSTL specification. The standard specifies

an input voltage range of – 0.3 V

≤VI ≤VCCIO + 0.3 V. The differential

HSTL I/O standard is only available on the input and output clocks. See

the Stratix Device Family Data Sheet section of the Stratix Device Handbook,

Volume 1 for the HSTL signaling characteristics

Differential SSTL-2 (Class I & II)

The differential SSTL-2 I/O standard is a 2.5-V memory bus standard

used for applications such as high-speed double data rate (DDR) SDRAM

interfaces. This standard defines the input and output specifications for

devices that operate in the SSTL-2 logic switching range of 0.0 to 2.5 V.

This standard improves operation in conditions where a bus must be

isolated from large stubs. The SSTL-2 standard specifies an input voltage

range of – 0.3 V

≤VI ≤VCCIO + 0.3 V. Stratix devices support both input

and output levels. The differential SSTL-2 I/O standard is only available

on output clocks. See the Stratix Device Family Data Sheet section of the

Stratix Device Handbook, Volume 1 for the SSTL-2 signaling characteristics.

Stratix Differential I/O Pin Location

The differential I/O pins are located on the I/O banks on the right and

left side of the Stratix device. Table 5–1 shows the location of the Stratix

device high-speed differential I/O buffers. When the I/O pins in the I/O

banks that support differential I/O standards are not used for high-speed

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