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型號(hào)：	EP1S30F780I6N
廠商：	Altera
文件頁(yè)數(shù)：	404/864頁(yè)
文件大?。?/td>	0K
描述：	IC STRATIX FPGA 30K LE 780-FBGA
產(chǎn)品培訓(xùn)模塊：	Three Reasons to Use FPGA's in Industrial Designs
產(chǎn)品變化通告：	Package Height Change 03/March/2008
標(biāo)準(zhǔn)包裝：	18
系列：	Stratix®
LAB/CLB數(shù)：	3247
邏輯元件/單元數(shù)：	32470
RAM 位總計(jì)：	3317184
輸入/輸出數(shù)：	597
電源電壓：	1.425 V ~ 1.575 V
安裝類(lèi)型：	表面貼裝
工作溫度：	-40°C ~ 100°C
封裝/外殼：	780-BBGA
供應(yīng)商設(shè)備封裝：	780-FBGA（29x29）

Altera Corporation

Stratix Device Handbook, Volume 2

June 2006

I/O Pad Placement Guidelines

The previous equation accounts for the input limitations, but you must

apply the appropriate equation from Table 4–9 to determine the output

limitations.

In addition to the pad placement guidelines, use the following guidelines

when working with VREF standards:

Each bank can only have a single VCCIO voltage level and a single

VREF voltage level at a given time. Pins of different I/O standards can

share the bank if they have compatible VCCIO values (see Table 4–12

for more details).

In all cases listed above, the Quartus II software generates an error

message for illegally placed pads.

Output Enable Group Logic Option in Quartus II

The Quartus II software can check a design to make sure that the pad

placement does not violate the rules mentioned above. When the

software checks the design, if the design contains more bidirectional pins

than what is allowed, the Quartus II software returns a fitting error. When

all the bidirectional pins are either input or output but not both (for

example, in a DDR memory interface), you can use the Output Enable

Group Logic

option. Turning on this option directs the Quartus II Fitter

to view the specified nodes as an output enable group. This way, the Fitter

does not violate the requirements for the maximum number of pins

driving out of a VREF bank when a voltaged-referenced input pin or

bidirectional pin is present.

In a design that implements DDR memory interface with dq, dqs and dm

pins utilized, there are two ways to enable the above logic options. You

can enable the logic options through the Assignment Editor or by adding

the following assignments to your project’s ESF file:

OPTIONS_FOR_INDIVIDUAL_NODES_ONLY

: OUTPUT_ENABLE_GROUP 1;

dqs : OUTPUT_ENABLE_GROUP 1;

Table 4–11. Bidirectional Pad Limitation Formulas (Multiple VREF Inputs & Outputs)

Package Type

Thermally enhanced FineLine BGA and

thermally enhanced BGA cavity up

<Total number of bidirectional pads> + <Total number of additional

output pads>

≤20 (per VREF pad)

non-thermally enhanced cavity up and

non-thermally enhanced FineLine BGA

<Total number of bidirectional pads> + <Total number of additional

output pads>

≤15 (per VREF pad)

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