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參數(shù)資料
| 型號(hào)： | EM6517 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 4位微控制器 |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER |
| 中文描述： | 4位單片機(jī)的小型通用紅外遙控器 |
| 文件頁(yè)數(shù)： | 38/66頁(yè) |
| 文件大小： | 762K |
| 代理商： | EM6517 |
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EM6517
FOR ENGINEERING ONLY
EM Microelectronic-Marin SA, 09/99, Rev. A/277
38
12 Supply Voltage Level Detector
The EM6517-1 has a built-in Supply Voltage Level Detector (SVLD) circuitry, such that the CPU can compare
the supply voltage against a pre-selected value. During sleep mode this function is inhibited.
The CPU activates the supply voltage level
detector by writing
VldStart
= 1 in the register
RegVldCntl
. The actual measurement starts on
the next Ck[9] rising edge and lasts during the
Ck[9] high period (2 ms at 32 KHz). The busy
flag
VldBusy
stays high from
VldStart
set
until
the measurement is finished. The worst case
time until the result is available is 1.5 Ck[9]
prescaler clock periods (32 KHz -> 6 ms). The
detection level must be defined in register
RegVldLevel
before the
VldStart
bit is set.
During the actual measurement (2 ms) the
device will draw an additional 5 μA of I
VDD
current. After the end of the measure the result
is available by inspection of the bit
VldResult
.
An interrupt
IRQVLD
is send to indicate the end
of measure. If the result is read 0, then the
power supply voltage was greater than the detection level value. If read 1, the power supply voltage was lower
than the detection level value. During each read while
Busy=1
the
VldResult
is not guaranteed. The interrupt
request can be masked (default) (
MaskIRQVLD
bit).
12.1 SVLD Register
Table 12.1.1 register
RegVldCntl
Bit
3
2
2
1
0
R*; VLDResult is not guaranteed while VLDBusy=1
Name
VLDResult
VLDStart
VLDBusy
VLDlevel1
VLDlevel0
Reset
0
0
0
0
0
R/W
R*
W
R
R/W
R/W
Description
Vld result flag
Vld start
Vld busy flag
Vld level selection
Vld level selection
Table 12.1.2 Voltage level detector value selecting
Level
Level1
Level2
Level3
Level3
VldLevel1
0
0
1
1
VldLevel0
0
1
0
1
Typical voltage level
2.2
2.5
3.0
3.0
Figure 28. SVLD Timing Diagram
VBAT =V
DD
Compare Level
Ck[9] (256 Hz)
CPU starts
measure
Busy Flag
Measure
1
0
Result
Read Result
SVLD > VBAT
SVLD < VBAT
CPU starts
measure
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