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| 型號： | EM6517 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 4位微控制器 |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER |
| 中文描述： | 4位單片機的小型通用紅外遙控器 |
| 文件頁數(shù)： | 15/66頁 |
| 文件大?。?/td> | 762K |
| 代理商： | EM6517 |
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EM6517
FOR ENGINEERING ONLY
EM Microelectronic-Marin SA, 09/99, Rev. A/277
15
7.2.2 Pull-up or Pull-down
Each of the input port terminals PA[3:0] has a resistor integrated which can be used either as pull-up or pull-
down resistor, depending on the selected metal mask options. See the port A metal mask chapter for details.
The pull resistor can be inhibited using the
NoPullPA[n]
bits in the register
OptNoPullPA.
Table 7.2.1. Pull-up or Pull-down Resistor on Port A Inputs
Option mask
Option mask
NoPullPA[n]
pull-up
MPAPU[n]
pull-down
MPAPD[n]
value
Action
no
no
x
no pull-up, no pull-down
no
yes
0
no pull-up, pull-down
no
yes
1
no pull-up, no pull-down
yes
no
0
pull-up, no pull-down
yes
no
1
no pull-up , no pull-down
yes
yes
x
not allowed*
* only pull-up or pull-down may be chosen on any port A terminal (one choice is excluding the other)
7.2.3 Software Test Variables
The port A terminals PA[2:0] are also used as input conditions for conditional software branches. Independent
of the
OPTDebIntPA
and the
OPTIntEdgPA.
These CPU inputs always have a debouncer.
- Debounced PA[0] is connected to CPU TestVar1.
- Debounced PA[1] is connected to CPU TestVar2.
- SWB signal SWBEmpty is connected to CPU TestVar3
7.2.4 Port A for 10-Bit Counter
The PA[0] and PA[3] inputs can be used as the clock input terminal for the 10 bit counter in "event count" mode.
As for the IRQ generation one can choose debouncer or direct input with the register
OPTDebIntPA
and non-
inverted or inverted input with the register
OPTIntEdgPA
. Debouncer input is always recommended.
7.3 Port A registers
Table 7.3.1 Register RegPA
Bit
3
2
1
0
*Direct read on port A terminal
Name
PAData[3]
PAData[2]
PAData[1]
PAData[0]
Reset
-
-
-
-
R/W
R*
R*
R*
R*
Description
PA[3] input status
PA[2] input status
PA[1] input status
PA[0] input status
Table 7.3.2 Register RegIRQMask1
Bit
3
2
1
0
Default "0" is: interrupt request masked, no new request stored
Name
Reset
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
MaskIRQPA[3]
MaskIRQPA[2]
MaskIRQPA[1]
MaskIRQPA[0]
Interrupt mask for PA[3] input
Interrupt mask for PA[2] input
Interrupt mask for PA[1] input
Interrupt mask for PA[0] input
with
n=0…3
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