
EM6517
FOR ENGINEERING ONLY
EM Microelectronic-Marin SA, 09/99, Rev. A/277
31
9.2 SWB Interactive send mode
In interactive SWB mode the reloading of the data transmission register
RegSWBuff
is performed by the
application program. This means that it is possible to have an unlimited length transmission data stream. However,
since the application program is responsible for reloading the data a continuous data stream can only be achieved
at Ck[11] or Ck[12] (1 KHz or 2 KHz) transmission speeds. For the higher transmission speeds a series of writes
must be programmed and the serial output clock will not be continuous.
Serial transmission using the interactive mode is detailed in Figure 24. Programming of the SWB in interactive is
achieved in the following manner:
Select the transmission clock speed using the bits
SWBFSel1
and
SWBFSel0
in the
RegSWBCntl
register.
Load the first nibble of data into the SWB data register
RegSWBuff
Start serial transmission by selecting the bit
SWBStart
in the register
RegSWBSizeH
register.
Once the data has been transferred into the serial transmission register a non maskable interrupt (SWBEmpty) is
generated and TestVar[3] goes high. The CPU goes in the interrupt routine, with the JPV3 as first instruction in the
routine one can immediately jump to the SWB update routine to load the next nibble to be transmitted into the
RegSWBuff
register. If this reload is performed before all the serial data is shifted out then the next nibble is
automatically transmitted. This is only possible at the transmission speeds of Ck[11] or Ck[12] due to the number of
instructions required to reload the register. At the higher transmission speeds of Ck[14] or Ck[15] (8 KHz or 16
KHz) the application must restart the serial transmission by writing the
SWBStart
in the
RegSWBSizeH
register
after writing the next nibble to the
RegSWBuff
register.
Each time the
RegSWBuff
register is written the "SWBbuffer empty interrupt" and TestVar[3
]
are cleared to "0".
For proper operation the
RegSWBuff
register must be written before the serial clock drops to low during sending
the last bit (MSB) of the previous data.
Figure 24 Interactive Serial Write Buffer transmission
After loading the last nibble in the
RegSWBuff
register a new interrupt is generated when this data is transferred to
an intermediate Shift Register. Precaution must be made in this case because the SWB will give repetitive
interrupts until the last data is sent out completely and the
SWBStart
bit goes low automatically. One possibility to
overcome this is to check in the Interrupt subroutine that the
SWBStart
bit went low before exiting interrupt. Be
careful because if
SWBStar
t bit is cleared by software, transmission is stopped immediately.
Using the SWB high impedance mask option in Interactive mode. As soon as one sets the start bit the SWB
outputs go to ‘0’ and SWB transfer starts. At the end of the transfer the SWB outputs go immediately back into
high impedance state.