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參數(shù)資料
| 型號(hào)： | ELANSC410 |
| 英文描述： | Single Synchronous Buck Pulse-Width Modulation (PWM) Controller; Temperature Range: 0°C to 70°C; Package: 16-QFN |
| 中文描述： | ElanSC410 - ElanSC410框圖 |
| 文件頁(yè)數(shù)： | 67/119頁(yè) |
| 文件大小： | 1167K |
| 代理商： | ELANSC410 |
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lanSC310 Microcontroller Data Sheet
51
PREL IMINARY
served for the coprocessor in a PC/AT system and is
unavailable on the lanSC310 microcontroller. The
other interrupts are available to external peripherals as
in the PC/AT architecture via the IRQ15, IRQ14,
IRQ12–IRQ9, IRQ7–IRQ3, and IRQ1 inputs. Other
sources of interrupts are SMI/NMI and the PIRQ1–
PIRQ0 inputs.
The lanSC310 microcontroller interrupt controller has
programmable sources for interrupts. These program-
mable sources are controlled by the configuration reg-
isters. For more information, see Chapter 4 of the
lanTMSC310 Microcontroller Programmer’s Refer-
ence Manual, order #20665.
The Interrupt controller provides interrupt information
to the lanSC310 microcontroller power management
unit to allow the monitoring of system activity. The
lanSC310 microcontroller power management unit
can then use the interrupt activity to control the Power
Management mode of the lanSC310 microcontroller.
For more information, see
lanTMSC310 Microcontrol-
ler Programmer’s Reference Manual, order #20665.
DMA Controller
The lanSC310 microcontroller DMA controller is func-
tionally compatible with the standard cascaded 8237
controller pair. Channels 0, 1, 2, and 3 are externally
available 8 bit channels. DMA Channel 4 is the cas-
cade channel. Channels 5, 6, and 7 are externally
available as 16 bit channels.
All the DMA channels are masked off on hardware
reset or when writing the DMA master reset register.
Note: To enable the master to percolate the request to
the CPU, you must also unmask the cascade channel
(0) on the master.
The lanSC310 microcontroller supports the power-
saving clock stop feature that causes the clock to the
DMA controller to stop except when actually needed to
perform a DMA transfer. For more information about
clock states and programmable clock frequencies, see
The lanSC310 microcontroller supports Single,
Block, and Demand transfer modes; however, soft-
ware-initiated DMA requests, Cascade mode for addi-
tional external DMA controllers, and Verify mode are
not supported.
For more information about the DMA controller, see the
lanTMSC310 Microcontroller Programmer’s Refer-
ence Manual, order #20665.
Counter/Timer
The lanSC310 microcontroller’s counter/timer is func-
tionally compatible with the 8254 device. A 3-channel,
general-purpose, 8254 compatible, 16-bit counter/
timer is integrated into the lanSC310 microcontroller.
It can be programmed to count in binary or in Binary
Coded Decimal (BCD). Each counter operates inde-
pendently of the other two and can be programmed for
operation as a timer or a counter. All three are con-
trolled from a common set of control logic, which pro-
vides controls to load, read, configure, and control
each counter.
All of the 8254 compatible counter/timer channels are
driven from a common clock that is internally generated
from the LS_PLL 1.1892-MHz output. The output of
Counter 0 is connected to IRQ0.
Additional Peripheral Controllers
The lanSC310 microcontroller also integrates three
other peripheral controllers commonly found in PCs,
but not considered part of the “core peripherals,”
namely a serial port or a Universal Asynchronous Re-
ceiver Transmitter (UART), a bidirectional and EPP-en-
hanced parallel port, and a real-time clock (RTC). See
Chapter 3 of the
lanTMSC310 Microcontroller Pro-
grammer’s Reference Manual, order #20665.
16450 UART
The lanSC310 microcontroller chip includes a UART,
providing lanSC310 microcontroller systems with a
serial port. This serial controller is fully compatible with
the industry-standard 16450. In handheld systems, this
port can connect to the pen input device or to a modem.
Real-Time Clock
The lanSC310 microcontroller contains a fully
146818A-compatible real-time clock (RTC) imple-
mented in a PC/AT-compatible fashion. The RTC
drives its interrupt to power-management logic.
The RTC block in the lanSC310 microcontroller con-
sists of a time-of-day clock with alarm and 100-year
calendar. The clock/calendar can be represented in bi-
nary or BCD. It has a programmable periodic interrupt,
and 114 bytes of general purpose static RAM (an ex-
tension of the 146818A standard, see the program-
me r ’ s r e f e r ence m anu al fo r m o r e de tail s ) .
Parallel Port
The lanSC310 microcontroller parallel port is func-
tionally compatible with the PS/2 parallel port. The
lanSC310 microcontroller parallel port interface pro-
vides the parallel port control outputs and status inputs,
and also the control signals for the parallel port data
buffers. The parallel port data path is external to the
lanSC310 microcontroller. This interface can be con-
figured to operate in either a Unidirectional (Normal)
mode or Bidirectional (EPP) mode.
The unidirectional parallel port requires only one exter-
nal component, the parallel port data latch. This latch is
used to latch the data from the data bus and drive the
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