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參數(shù)資料
| 型號(hào)： | ELANSC410 |
| 英文描述： | Single Synchronous Buck Pulse-Width Modulation (PWM) Controller; Temperature Range: 0°C to 70°C; Package: 16-QFN |
| 中文描述： | ElanSC410 - ElanSC410框圖 |
| 文件頁(yè)數(shù)： | 61/119頁(yè) |
| 文件大小： | 1167K |
| 代理商： | ELANSC410 |
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46
lanSC310 Microcontroller Data Sheet
PREL IMINARY
asserted Low and PMC3 is asserted High. Prior to this
edge, these signals are undefined.
The lanSC310 microcontroller can be programmed to
reset a timer when an I/O access to a preset address
range is detected. If no I/O activity in that range occurs
before the timer expires, the lanSC310 microcontrol-
ler can assert a PMC signal to turn off the device. When
software accesses that address range later, the
lanSC310 microprocessor can generate a System
Management Interrupt (SMI) to the processor, which
then activates an SMI handler routine. This routine
then can determine the cause of the SMI and take ap-
propriate action, such as powering the I/O device back
on.
The PGP3–PGP0 pins are controlled by several config-
uration registers (70h, 74h, 89h, 91h, 94h, 95h, 9Ch,
A3h, and A4h) and their behavior is very flexible. PGP0
and PGP1 can be programmed as input or output.
PGP2 and PGP3 are dedicated outputs. PGP1 and
PGP3 can be gated with I/O reads, PGP0 and PGP2
can be gated with I/O writes, or each can act as an ad-
dress decode for a chip select.
Micro Power Off Mode
Micro Power Off mode is the power management mode
that is used for battery backup.
Micro Power Off mode allows the system designer to
remove power from the VCC1, VSYS, VSYS2, and
VCC5 power inputs to the microcontroller. This allows
the RTC timer and RAM contents to be kept valid by
using a battery back-up power source on the VCC core
and AVCC pins, which typically should use only 25
A
in this mode.
The following paragraphs describe the lanSC310 mi-
crocontroller in Micro Power Off mode. The following
are distinctive characteristics:
n Minimum Power Consumption mode (approxi-
mately 25
A typical, AVCC, and Core VCC com-
bined; AVCC and VCC are mandatory for Micro
Power Off mode).
n Allows the system designer to utilize the internal
RTC and RTC RAM to maintain time, date, and
system configuration data while the other system
peripherals are powered off.
n Provides the system designer with the option of
keeping the system DRAM powered and refreshed
while other system peripherals are powered off.
Self-refresh and CAS-before-RAS refresh DRAMs
are supported.
n Minimal external logic required to properly control
power supplies and/or power switching.
n No external buffering required to properly power
down system hardware.
The lanSC310 microcontroller allows a system de-
signer to easily maintain the internal RTC and RTC
RAM and optionally, the DRAM interface, while the rest
of the system peripherals attached directly to the de-
vice are powered off. All lanSC310 microcontroller
power pins associated with the I/O pins of external
powered-off peripherals must be powered down also.
This, in addition to internal termination, provides the re-
quired isolation to allow the external peripherals to be
powered off.
Automatically controlled internal I/O termination is pro-
vided to terminate the internal nodes of the lanSC310
microcontroller properly when required.
The DRAM CAS-before-RAS, or self-refresh, can be
maintained by the lanSC310 microcontroller in this
Micro Power State, if configured to do so, utilizing the
32-kHz oscillator. This clock continues to drive the RTC
and a portion of the core logic. See the
lanTMSC300
and lanTMSC310 Microcontrollers Solution For Sys-
tems Using a Back-up Battery Application Note, order
#20746 for more information about the 32-kHz oscilla-
tor and the RTC. The VMEM power plane (DRAM/
SRAM section power) must remain powered on if the
CAS-before-RAS refresh option is selected while in the
Micro Power state. The VMEM power plane must also
remain powered on if the self-refresh option is selected
and the specific DRAM device requires any of its con-
trol pins (i.e., WE, CAS, RAS, etc.) to remain inactive in
the Self-Refresh mode. If this is not required, it may be
possible for the system designer to remove power from
the VMEM pins when entering the Micro Power state,
even if the Self-Refresh mode DRAMs remain powered
on.
A portion of a typical system using a secondary power
supply to maintain the RTC and RTC RAM (and option-
ally system DRAM) is shown in Figure 3 on page 47.
This secondary power supply could be as simple as a
small lithium coin cell battery as indicated in the dia-
gram, but is certainly not limited to this. Note that when
all primary power supply outputs are turned off, all of
the system’s peripherals are powered off (DRAM op-
tional), all of the lanSC310 microcontroller’s power
planes are powered off except AVCC (analog) and
VCC (core), and the secondary power supply is
“switched in” to maintain the lanSC310 microcontrol-
ler’s core and analog power source.
For more information about back-up batteries, see the
lanTMSC300 and lanTMSC310 Micrcontrollers Solu-
tion For Systems Using a Back-Up Battery Application
Note, order #20746.
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相關(guān)代理商/技術(shù)參數(shù) |
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| ELANSC410-100AC | 制造商:Advanced Micro Devices 功能描述:MCU 16-Bit/32-Bit Elan CISC ROMLess 3.3V 292-Pin BGA |
| ELANSC410-100ACAD | 制造商:Advanced Micro Devices 功能描述: |
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| ELANSC410-33AI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers |
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