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參數(shù)資料
| 型號： | ELANSC410 |
| 英文描述： | Single Synchronous Buck Pulse-Width Modulation (PWM) Controller; Temperature Range: 0°C to 70°C; Package: 16-QFN |
| 中文描述： | ElanSC410 - ElanSC410框圖 |
| 文件頁數(shù)： | 62/119頁 |
| 文件大小： | 1167K |
| 代理商： | ELANSC410 |
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lanSC310 Microcontroller Data Sheet
47
PREL IMINARY
The RESIN pin acts as the master reset. When active,
all of the internal components are reset, including the
RTC, and the RTC RAM invalid bit will be set. This
causes an issue with the power-loss bit (VRT), Index
0Dh, bit 7 of the RTC map. The VRT bit is intended to
provide a method of determining when the RTC core
voltage supply has dropped below an acceptable level.
On a 146818A-compatible device, anything below
2.4 V will cause a low-battery condition and will cause
the power-loss bit to go Low. On the lanSC310 micro-
controller, the 32-KHz clock used by RTC to maintain
time stops oscillating before the VRT bit or RAM con-
tents get cleared because the VRT bit will only get
cleared when the RESIN pin is asserted Low. Thus, the
RTC time will be inaccurate even though the RAM con-
tents are valid and the VRT bit is still set.
Note: Although the 32-KHz clock stops oscillating be-
fore the power-loss bit is cleared, this event occurs well
before the 2.4-V specification for proper lanSC310
microcontroller functionality.
The RESIN pin should only be asserted (pulsed) Low
when a power source is initially applied to the device’s
core and analog sections.
For more information about these notes, see the
lanTMSC300 and lanTMSC310 Microcontrollers Solu-
tion For Systems Using a Back-up Battery Application
Note
, order #20746.
The IORESET signal is intended to be the normal
“POWER GOOD” status from the primary power supply
in the example design shown in Figure 3. The IORE-
SET input does not reset the RTC and will not set the
RTC RAM invalid bit.
IORESET (when the inactive state is detected) will
cause the lanSC310 microcontroller to go through its
power-up sequence including PLL start-up for clock
generation and an internal CPU reset. See Figure 32
through Figure 35, beginning on page 89, for the initial
power-up timing requirements and for Micro Power
mode exit timing.
When entering Micro Power Off mode and the primary
power supply outputs are turned off, all of the
lanSC310 microcontroller’s powered-down I/O pins
are essentially tri-stated and the internal pull-ups are
removed because the VCCIO and VCC CLAMP of the
output driver have been removed, as shown in Figure
34 on page 91. This provides the ability to power off ex-
ternal peripherals that are attached directly to the
lanSC310 microcontroller without concern of driving
current into the pins of the external powered-down de-
vice.
To assure that the lanSC310 microcontroller does not
draw excessive power while in this state, internal pull-
down resistors will be enabled. Enabling these resis-
tors keeps the input buffers from floating (see Figure 4).
On/Off
ACIN
lanSC310
Microcontroller
RTC
PMU
Power Supply
Swapping
Circuit
Primary
Power
Supply
Secondary
Power Supply
IORESET
M
E
M
O
R
Y
L
O
C
A
L
Main
Battery
+
-
3.3 V
5 V
Parallel/Serial
Power Management
Analog
ISA/LOCAL
ISA
ISA and Misc.
RESIN
R
C
VCC
(Core)
AVCC
Figure 3.
Typical System Design with Secondary Power Supply to Maintain RTC When
Primary Power Supply is Off (DRAM Refresh is Optional.)
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