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參數(shù)資料
| 型號(hào)： | ELANSC410 |
| 英文描述： | Single Synchronous Buck Pulse-Width Modulation (PWM) Controller; Temperature Range: 0°C to 70°C; Package: 16-QFN |
| 中文描述： | ElanSC410 - ElanSC410框圖 |
| 文件頁數(shù)： | 3/119頁 |
| 文件大小： | 1167K |
| 代理商： | ELANSC410 |
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100
lanSC310 Microcontroller Data Sheet
PREL IMINARY
Notes:
Fast ROM cycles, see the lanTMSC300 and lanTMSC310 Devices’ ISA Bus Anomalies Application Note, order #20747.
1. This is the timing when ROMCS is qualified with MEMR or MEMW, (Bit 2 of the Miscellaneous 5 Register, Index B3h, = 0).
2. This is the timing when ROMCS is configured as an address decode, (Bit 2 of the Miscellaneous 5 Register, Index B3h, = 1).
These timings are based on default wait state settings, set for 3 wait states in bits 4 and 7 of the Command Delay Register, Index
60h, and required initial programming. These timings may be modified via the MMS Memory Wait State 1 Register, Index 62H,
and the Command Delay Register, Index 60H. (See the lanTMSC310 Microcontroller Programmer’s Reference Manual, order
#20665.
)
For Fast ROMCS (BIOS ROM) accesses, set bit 6 of Miscellaneous 5 Register, Index B3h. Bits 4 and 5 control wait states when
Fast ROMCS is enabled. For 16-bit Fast ROMCS timings with the default wait state settings of 4 wait states, see Table 54. For
more information about
Table 52.
BIOS ROM Read/Write 8 Bit Cycle (See Figure 41)
Symbol
Parameter Description
Notes
Preliminary
Units
Min
Max
t1a
SA stable to ROMCS active
1
55
ns
t1b
SA stable to ROMCS active
2
5
ns
t2a
SA hold from ROMCS inactive (write)
1
50
ns
t2b
SA hold from ROMCS inactive (read)
1
0
ns
t3a
ROMCS pulse width (read)
1
390
ns
t3b
ROMCS pulse width (write)
1
335
ns
t4a
MEMW active to ROMCS active
1
2
ns
t4b
MEMR active to ROMCS active
1
ns
t5a
ROMCS hold from MEMW inactive
1
0
ns
t5b
ROMCS hold from MEMR inactive
1
0
ns
t6
RDDATA setup to command inactive
40
ns
t7
RDDATA hold from command inactive
0
ns
t8
WRDATA setup to command inactive
200
ns
t9
WRDATA hold from command inactive
50
ns
t10
DBUFOE active from command
5
ns
t11a
DBUFOE hold from MEMW
50
ns
t11b
DBUFOE hold from MEMR
–2
ns
t12
ENDIRH, ENDIRL setup before MEMR
50
ns
t13
ENDIRH, ENDIRL hold from MEMR
–4
ns
t14
ROMCS active to command active
2
65
ns
t15
ROMCS hold from SA
2
5
ns
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ELANSC410-100AC | 制造商:Advanced Micro Devices 功能描述:MCU 16-Bit/32-Bit Elan CISC ROMLess 3.3V 292-Pin BGA |
| ELANSC410-100ACAD | 制造商:Advanced Micro Devices 功能描述: |
| ELANSC410-100AI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers |
| ELANSC410-33AC | 制造商:Advanced Micro Devices 功能描述:MCU 16-Bit/32-Bit Elan CISC 3.3V 292-Pin BGA |
| ELANSC410-33AI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers |
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