- 您現在的位置：買賣IC網 > PDF目錄97907 > ELANSC410 Single Synchronous Buck Pulse-Width Modulation (PWM) Controller; Temperature Range: 0°C to 70°C; Package: 16-QFN PDF資料下載
參數資料
| 型號： | ELANSC410 |
| 英文描述： | Single Synchronous Buck Pulse-Width Modulation (PWM) Controller; Temperature Range: 0°C to 70°C; Package: 16-QFN |
| 中文描述： | ElanSC410 - ElanSC410框圖 |
| 文件頁數： | 46/119頁 |
| 文件大?。?/td> | 1167K |
| 代理商： | ELANSC410 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁當前第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁
32
lanSC310 Microcontroller Data Sheet
PREL IMINARY
IRQ1, IRQ14
Interrupt Request Channels 1 and 14 (Input; Rising
Edge/Active High, with Internal Pullup)
This input is connected to the internal 8259A-compati-
ble Interrupt Controller Channels 1 and 14. In PC-com-
patible systems, IRQ1 may be connected to the 8042
keyboard controller.
MCS16
(Input; Active Low)
This input is used to signal to the ISA control logic that
the targeted memory device is a 16-bit device.
MCS16
is generated by a 16-bit memory expansion
card when the card recognizes it is being addressed.
This signal tells the data bus steering logic that the ad-
dressed memory device is capable of communicating
over both data paths. When accessing an 8-bit memory
device, the MCS16 line remains deasserted, indicating
to the data bus steering logic that the currently ad-
dressed device is an 8-bit memory device capable of
communicating only over the lower data path.
Note: MCS16 is internally OR’d with IOCS16. Do not tie
MCS16
Low.
For more information about the MCS16 pin, see the
Using 16-Bit ROMCS Designs in lanTMSC300 and
lanSC310 Microcontrollers Application Note, order
#21825.
MEMR
Memory Read Command (Output; Active Low)
The MEMR signal indicates that the current cycle is a
read of the currently selected memory device. When
this signal is asserted, the selected memory device can
drive data onto the data bus.
MEMW
Memory Write Command (Output; Active Low)
The MEMW signal indicates that the current cycle is a
write of the currently selected memory device. When
this signal is asserted, the selected memory device can
latch data from the data bus.
PIRQ0 (IRQ6)
PIRQ1 (IRQ3)
Programmable Interrupt Requests (Inputs; Rising
Edge/Active High, with Internal Pullup)
These two inputs can be programmed to drive any of
the available interrupt controller interrupt request in-
puts. For more information, see the corresponding
PIRQ Configuration Register, Index B2h, in the
lanTMSC310 Microcontroller Programmer’s Refer-
ence Manual, order #20665.
RSTDRV
System Reset (Output; Active High)
This signal is the ISA-compatible reset signal. When
this signal is asserted, all connected devices reinitialize
to their reset state. The pulse width of RSTDRV is ad-
justable based on PLL startup timings. For more infor-
mation, see “Loop Filters” on page 86 and the power-
up sequence timings beginning on page 88.
SA11–SA0
System Address Bus (Output; Active High)
The system address bus outputs the physical memory
or I/O port, least-significant, latched addresses. They
are used by all external I/O devices and all memory de-
vices other than main system DRAM. During main sys-
tem SRAM and local bus cycles, this bus represents
the CPU address bus (A11–A1). SA0 is equivalent to
A0 during local bus cycles. See MA11–MA0 on
page 30 for SA23–SA12.
SBHE
(Output; Active Low)
Active when the high byte is to be transferred on the
upper 8 bits of the data bus.
SPKR
Speaker, Digital Audio Output (Output)
This signal controls an external speaker driver. It is
generated from the internal 8254-compatible Timer
Channel 2 output ANDed with I/O port 061h, bit 1
(speaker data enable).
TC [TMS]
Terminal Count (Output; Active High)
This signal is used to indicate that the transfer count for
the currently active DMA channel has reached zero,
and that the current DMA cycle is the last transfer.
This is a dual-function pin. When the JTAGEN signal is
asserted, it will function as the TMS, JTAG Test Mode
Select pin. See the JTAG Interface section for more in-
formation on the function of this pin during Test mode.
KEYBOARD INTERFACE
8042CS [XTDAT]
Keyboard Controller Chip Select (Output; Active Low)
This signal is a decode of A9–A0 = 060h to 06Eh, all
even addresses. In PC-compatible systems, it con-
nects to the external keyboard controller chip select.
XTDAT is the PC/XT keyboard data line.
A20GATE
Address Bit-20 Gate (Input; Active High)
When deasserted (Low), A20GATE is used to force
CPU address bit 20 Low, a function required for PC
相關PDF資料 |
PDF描述 |
|---|---|
| ELH0032G | Fast Operational Amplifier |
| ELH0033G | Fast Buffer Amplifier |
| ELH0101CK | Dual Regulator-Standard Buck PWM and Linear Power Controller; Temperature Range: 0°C to 70°C; Package: 8-SOIC T&R |
| ELH0101ACK | Single Synchronous Buck Pulse-Width Modulation (PWM) Controller; Temperature Range: -40°C to 85°C; Package: 16-QFN |
| ELH0101 | Power Operational Amplifier |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ELANSC410-100AC | 制造商:Advanced Micro Devices 功能描述:MCU 16-Bit/32-Bit Elan CISC ROMLess 3.3V 292-Pin BGA |
| ELANSC410-100ACAD | 制造商:Advanced Micro Devices 功能描述: |
| ELANSC410-100AI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers |
| ELANSC410-33AC | 制造商:Advanced Micro Devices 功能描述:MCU 16-Bit/32-Bit Elan CISC 3.3V 292-Pin BGA |
| ELANSC410-33AI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers |
發(fā)布緊急采購，3分鐘左右您將得到回復。