參數(shù)資料
型號(hào): DSPB56007FJ50
英文描述: DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC
中文描述: 數(shù)字信號(hào)處理器| 24位|的CMOS | QFP封裝| 80腳|塑料
文件頁(yè)數(shù): 41/83頁(yè)
文件大?。?/td> 382K
代理商: DSPB56007FJ50
Specifications
External Memory Interface (EMI) SRAM Timing
MOTOROLA
DSP56007/D
2-17
EXTERNAL MEMORY INTERFACE (EMI) SRAM TIMING
(C
L
= 50pF + 2 TTL Loads)
Figure 2-12
CAS before RAS Refresh Cycle
Table 2-10
External Memory Interface (EMI) SRAM Timing
No.
Characteristics
Symbol
Expression
50 MHz
66 MHz
88 MHz
Unit
Min Max Min Max Min Max
91 Address Valid and CS
Assertion Pulse Width
92 Address Valid to RD or WR
Assertion
93 RD or WR Assertion Pulse
Width
94 RD or WR Deassertation to
RD or WR Assertion
95 RD or WR Deassertation to
Address not Valid
96 Address Valid to Input Data
Valid
97 RD Assertion to Input Data
Valid
98 RD Deassertation to Data
Not Valid (Data Hold Time)
t
RC
, t
WC
4
×
T
C
– 11 +
Ws
×
T
C
T
C
+ T
L
– 13
69
50
34.5
ns
t
AS
17
10
4.4
ns
t
WP
2
×
T
C
– 5 +
Ws
×
T
C
2
×
T
C
– 11
35
23
17.7
ns
29
19
11.7
ns
t
WR
T
H
– 6
4
2
0.1
ns
t
AA
, t
AC
3
×
T
C
+ T
L
–15 +
Ws
×
T
C
2
×
T
C
– 15 +
Ws
×
T
C
0
55
38
24.8
ns
t
OE
25
15
7.7
ns
t
OHZ
0
0
0
ns
MRAS
MCAS
Data In
MD0–MD7
83
81
84
85
88
82
87
89
86
AA0266
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