參數(shù)資料
型號： DSPB56007FJ50
英文描述： DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC
中文描述： 數(shù)字信號處理器| 24位|的CMOS | QFP封裝| 80腳|塑料
文件頁數(shù)： 18/83頁
文件大小： 382K
代理商： DSPB56007FJ50
1-12
DSP56007/D
MOTOROLA
Signal/Connection Descriptions
Serial Host Interface (SHI)
SS
HA2
Input
Input
Tri-stated
SPI Slave Select (SS)
—This signal is an active low
Schmitt-trigger input when configured for the SPI
mode. When configured for the SPI Slave mode, this
signal is used to enable the SPI slave for transfer.
When configured for the SPI Master mode, this
signal should be kept deasserted. If it is asserted
while configured as SPI master, a bus error
condition will be flagged.
I
2
C Slave Address 2 (HA2)
—This signal uses a
Schmitt-trigger input when configured for the I
2
C
mode. When configured for the I
2
C Slave mode, the
HA2 signal is used to form the slave device address.
HA2 is ignored in the I
2
C Master mode. If SS is
deasserted, the SHI ignores SCK clocks and keeps
the MISO output signal in the high-impedance
state.
Note:
This signal is tri-stated during hardware reset,
software reset, or individual reset (no need for
external pull-up in this state).
HREQ
Input or
Output
Tri-stated
Host Request
—This signal is an active low Schmitt-
trigger input when configured for the Master mode, but
an active low output when configured for the Slave
mode. When configured for the Slave mode, HREQ is
asserted to indicate that the SHI is ready for the next data
word transfer and deasserted at the first clock pulse of
the new data word transfer. When configured for the
Master mode, HREQ is an input and when asserted by
the external slave device, it will trigger the start of the
data word transfer by the master. After finishing the data
word transfer, the master will await the next assertion of
HREQ to proceed to the next transfer.
Note:
This signal is tri-stated during hardware, software,
individual reset, or when the HREQ[1:0] bits (in the
HCSR) are cleared (no need for external pull-up in this
state).
Table 1-8
Serial Host Interface (SHI) signals (Continued)
Signal Name
Signal
Type
State
during
Reset
Signal Description
相關(guān)PDF資料
PDF描述
DSPB56007FJ66 DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC
DSPB56007FJ88 DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC
DSPE56007FJ50 DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC
DSPE56007FJ66 DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC
DSPE56007FJ88 DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSPB56007FJ66 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC
DSPB56007FJ88 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC
DSPB56011 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:24-BIT DVD DIGITAL SIGNAL PROCESSOR
DSPB56362AG120 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC LEAD FREE DSP56362 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSPB56362AG120 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*