參數(shù)資料
型號: DSPB56007FJ50
英文描述: DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC
中文描述: 數(shù)字信號處理器| 24位|的CMOS | QFP封裝| 80腳|塑料
文件頁數(shù): 35/83頁
文件大?。?/td> 382K
代理商: DSPB56007FJ50
Specifications
External Memory Interface (EMI) DRAM Timing
MOTOROLA
DSP56007/D
2-11
64 Random Read or Write
Cycle Time (Single
Access Only)
65 WR Deassertation to
CAS Assertion
66 CAS Assertion to WR
Deassertation
67 Data Valid to CAS
Assertion
(Data Setup Time)
68 CAS Assertion to Data
Not Valid (Data Hold
Time)
t
RC
slow
fast
12
×
T
C
8
×
T
C
240
98.8
182
121
136.4
91.0
ns
ns
t
RCS
slow
fast
slow
fast
9
×
T
C
– 11
6
×
T
C
– 11
3
×
T
C
– 13
2
×
T
C
– 13
T
L
– 6
169
109
47
27
4
125
80
32
17
2
91.3
57.2
21.1
9.7
0.1
ns
ns
ns
ns
ns
t
WCH
t
DS
t
DH
slow
fast
3
×
T
C
+ T
H
14
2
×
T
C
+ T
H
14
7
×
T
C
+ T
H
14
5
×
T
C
+ T
H
14
4
×
T
C
– 14
3
×
T
C
– 14
7
×
T
C
– 9
5
×
T
C
– 9
56
36
39
24
25.8
14.4
ns
ns
69 RAS Assertion to Data
Not Valid
t
DHR
slow
fast
136
96
100
69
71.2
48.5
ns
ns
70 WR Assertion to CAS
Assertion
71 WR Assertion Pulse
Width (Single Cycle
Only)
72 RAS Assertion to WR
Deassertation
(Single Cycle Only)
73 WR Assertion to Data
Active
t
WCS
slow
fast
slow
fast
66
46
131
91
47
31
97
67
31.4
20.1
70.5
47.8
ns
ns
ns
ns
t
WP
t
WCR
slow
fast
7
×
T
C
– 15
5
×
T
C
– 15
125
85
91
61
64.5
41.8
ns
ns
slow
fast
3
×
T
C
+ T
H
13
2
×
T
C
+ T
H
13
7
×
T
C
– 13
5
×
T
C
– 13
57
37
40
25
26.8
15.4
ns
ns
74 RD or WR Assertion to
RAS Deassertation
(Single Cycle Only)
t
ROH
,
t
RWL
slow
fast
127
87
93
63
66.5
43.8
ns
ns
Note:
1.
n is the number of successive accesses. n = 2, 3, 4, or 6.
Table 2-8
External Memory Interface (EMI) DRAM Timing (Continued)
No.
Characteristics
Symbol
Timing
Mode
Expression
50 MHz
66 MHz
88 MHz
Unit
Min Max Min Max Min Max
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