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參數(shù)資料
| 型號： | DSPB56007FJ50 |
| 英文描述： | DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC |
| 中文描述： | 數(shù)字信號處理器| 24位|的CMOS | QFP封裝| 80腳|塑料 |
| 文件頁數(shù)： | 11/83頁 |
| 文件大?。?/td> | 382K |
| 代理商： | DSPB56007FJ50 |
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Signal/Connection Descriptions
External Memory Interface (EMI)
MOTOROLA
DSP56007/D
1-5
EXTERNAL MEMORY INTERFACE (EMI)
Table 1-5
External Memory Interface (EMI) Signals
Signal Name
Signal
Type
State during
Reset
Signal Description
MA0–MA14
Output
Table 1-6
Memory Address Lines 0–14
—The MA0–MA10 lines provide
the multiplexed row/ column addresses for DRAM accesses.
Lines MA0–MA14 provide the non-multiplexed address lines
0–14 for SRAM accesses.
MA15
MCS3
Output
Table 1-6
Memory Address Line 15 (MA15)
—This line functions as the
non-multiplexed address line 15.
Memory Chip Select 3 (MCS3)
—For SRAM accesses, this line
functions as memory chip select 3.
MA16
MCS2
MCAS
Output
Table 1-6
Memory Address Line 16 (MA16)
—This line functions as the
non-multiplexed address line 16 or as memory chip select 2 for
SRAM accesses.
Memory Chip Select 2 (MCS2)
—For SRAM access, this line
functions as memory chip select 2.
Memory Column Address Strobe (MCAS)
—This line
functions as the Memory Column Address Strobe (MCAS)
during DRAM accesses.
MA17
MCS1
MRAS
Output
Table 1-6
Memory Address Line 17 (MA17)
—This line functions as the
non-multiplexed address line 17.
Memory Chip Select 1 (MCS1)—
This line functions as chip
select 1 for SRAM accesses.
Memory Row Address Strobe (MRAS)
—This line also
functions as the Memory Row Address Strobe during DRAM
accesses.
MCS0
Output
Table 1-6
Memory Chip Select 0
—This line functions as memory chip
select 0 for SRAM accesses.
MWR
Output
Table 1-6
Memory Write Strobe
—This line is asserted when writing to
external memory.
MRD
Output
Table 1-6
Memory Read Strobe
—This line is asserted when reading
external memory.
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| DSPB56007FJ66 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC |
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| DSPB56362AG120 | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor |
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