參數(shù)資料
型號: DSP56F805
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: 16-bit Hybrid Controller(16位混合控制器)
中文描述: 16位混合控制器(16位混合控制器)
文件頁數(shù): 9/48頁
文件大?。?/td> 967K
代理商: DSP56F805
Address, Data, and Bus Control Signals
56F805 Technical Data
9
2.4 Address, Data, and Bus Control Signals
1
CLKO
Output
Chip-driven
Clock Output
—This pin outputs a buffered clock signal. By
programming the CLKOSEL[4:0] bits in the CLKO Select
Register (CLKOSR), the user can select between outputting a
version of the signal applied to XTAL and a version of the
device’s master clock at the output of the PLL. The clock
frequency on this pin can also be disabled by programming the
CLKOSEL[4:0] bits in CLKOSR.
Table 7. Address Bus Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
6
A0–A5
Output
Tri-stated
Address Bus
—A0–A5 specify the address for external
Program or Data memory accesses.
2
A6–A7
GPIOE2
GPIOE3
Output
Input/
Output
Tri-stated
Input
Address Bus
—A6–A7 specify the address for external
Program or Data memory accesses.
Port E GPIO
—These two General Purpose I/O (GPIO) pins
can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
8
A8–A15
GPIOA0
GPIOA7
Output
Input/
Output
Tri-stated
Input
Address Bus
—A8–A15 specify the address for external
Program or Data memory accesses.
Port A GPIO
—These eight General Purpose I/O (GPIO) pins
can be individually be programmed as input or output pins.
After reset, the default state is Address Bus.
Table 8. Data Bus Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
16
D0–D15
Input/
Output
Tri-stated
Data Bus
— D0–D15 specify the data for external Program or
Data memory accesses. D0–D15 are tri-stated when the external
bus is inactive. Internal pullups may be active.
Table 6. PLL and Clock (Continued)
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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