參數(shù)資料
型號(hào)： DSP56F805
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Hybrid Controller(16位混合控制器)
中文描述： 16位混合控制器（16位混合控制器）
文件頁(yè)數(shù)： 24/48頁(yè)
文件大?。?/td> 967K
代理商： DSP56F805
24
56F805 Technical Data
Figure 8. Flash Mass Erase Cycle
3.5 External Clock Operation
The 56F805 system clock can be derived from a crystal or an external system clock signal. To generate a
reference frequency using the internal oscillator, a reference crystal must be connected between the
EXTAL and XTAL pins.
3.5.1
Crystal Oscillator
The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the
frequency range specified for the external crystal in
Table 28
. In
Figure 9
a recommended crystal
oscillator circuit is shown. Follow the crystal supplier’s recommendations when selecting a crystal,
because crystal parameters determine the component values required to provide maximum stability and
reliable start-up. The crystal and associated components should be mounted as close as possible to the
EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. The internal 56F80x
oscillator circuitry is designed to have no external load capacitors present. As shown in
Figure 10
no
external load capacitors should be used.
The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a
capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and
process variations. Using a typical value of internal capacitance on these pins of 12pF and a value of 3pF as
a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as
determined by the following equation:
XADR
YE=SE=OE=0
ERASE
NVSTR
Tnvs
Tnvh1
Trcv
Tme
MAS1
IFREN
XE
CL =
CL1 * CL2
CL1 + CL2
+ Cs =
+ 3 = 6 + 3 = 9pF
12 * 12
12 + 12
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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