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參數(shù)資料
| 型號(hào)： | DSP56F805 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 16-bit Hybrid Controller(16位混合控制器) |
| 中文描述： | 16位混合控制器（16位混合控制器） |
| 文件頁數(shù)： | 38/48頁 |
| 文件大?。?/td> | 967K |
| 代理商： | DSP56F805 |
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38
56F805 Technical Data
Figure 29. Equivalent Analog Input Circuit
1.
2.
3.
4.
Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)
Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)
Equivalent resistance for the ESD isolation resistor and the channel select mux. ( 500 ohms)
Sampling capacitor at the sample and hold circuit. (1pf)
3.13 Controller Area Network (CAN) Timing
Figure 30. Bus Wakeup Detection
Table 36. CAN Timing
2
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40
°
to +85
°
C, C
L
≤
50pF, MSCAN Clock = 30MHz
Characteristic
Symbol
Min
Max
Unit
Baud Rate
BR
CAN
—
1
Mbps
Bus Wakeup detection
1
1.
event (on MSCAN_RX pin) whose duration is less than 5 microseconds is filtered away. However, a valid CAN bus
wakeup detection takes place for a wakeup pulse equal to or greater than 5 microseconds. The number 5 microseconds
originates from the fact that the CAN wakeup message consists of 5 dominant bits at the highest possible baud rate of
1Mbps.
2.
Parameters listed are guaranteed by design.
If Wakeup glitch filter is enabled during the design initialization and also CAN is put into Sleep mode then, any bus
T
WAKEUP
5
—
us
1
2
3
4
ADC analog input
MSCAN_RX
CAN receive
data pin
(Input)
T
WAKEUP
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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