參數(shù)資料
型號(hào)： DSP56F805
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Hybrid Controller(16位混合控制器)
中文描述： 16位混合控制器（16位混合控制器）
文件頁(yè)數(shù)： 26/48頁(yè)
文件大?。?/td> 967K
代理商： DSP56F805
26
56F805 Technical Data
Figure 12. External Clock Timing
3.5.4
Phase Locked Loop Timing
Table 27. External Clock Operation Timing Requirements
3
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6V, T
A
= –40
°
to +85
°
C
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation (external clock driver)
1
1.
2.
3.
See
Figure 11
for details on using the recommended connection of an external clock driver.
The high or low pulse width must be no smaller than 6.25ns or the chip will not function.
Parameters listed are guaranteed by design.
f
osc
0
—
80
MHz
Clock Pulse Width
2
,
5
t
PW
6.25
—
—
ns
Table 28. PLL Timing
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6V, T
A
= –40
°
to +85
°
C
Characteristic
Symbol
Min
Typ
Max
Unit
External reference crystal frequency for the PLL
1
1.
correctly. The PLL is optimized for 8MHz input crystal.
2.
ZCLK may not exceed 80MHz. For additional information on ZCLK and
f
out
/2,
please refer to the OCCS chapter
in the User Manual. ZCLK = f
op
3.
This is the minimum time required after the PLL set-up is changed to ensure reliable operation.
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
f
osc
4
8
10
MHz
PLL output frequency
2
f
out
/2
40
—
110
MHz
PLL stabilization time
3
0
o
to +85
o
C
t
plls
—
1
10
ms
PLL stabilization time
3
-40
o
to 0
o
C
t
plls
—
100
200
ms
External
Clock
V
IH
V
IL
Note: The midpoint is V
IL
+ (V
IH
– V
IL
)/2.
90%
50%
10%
90%
50%
10%
t
PW
t
PW
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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