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參數(shù)資料
| 型號(hào)： | DSP56F805 |
| 廠(chǎng)商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | 16-bit Hybrid Controller(16位混合控制器) |
| 中文描述： | 16位混合控制器（16位混合控制器） |
| 文件頁(yè)數(shù)： | 15/48頁(yè) |
| 文件大?。?/td> | 967K |
| 代理商： | DSP56F805 |
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Quad Timer Module Signals
56F805 Technical Data
15
2.13 Quad Timer Module Signals
2.14 JTAG/OnCE
Table 18. Quad Timer Module Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
2
TC0-1
Input/
Output
Input
TC0
–
1
—Timer C Channels 0 and 1
4
TD0-3
Input/
Output
Input
TD0
–
3
—Timer D Channels 0, 1, 2, and 3
Table 19. JTAG/On-Chip Emulation (OnCE) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
TCK
Input
(Schmitt)
Input, pulled
low internally
Test Clock Input
—This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/OnCE
port. The pin is connected internally to a pull-down resistor.
1
TMS
Input
(Schmitt)
Input, pulled
high internally
Test Mode Select Input
—This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
1
TDI
Input
(Schmitt)
Input, pulled
high internally
Test Data Input
—This input pin provides a serial input data stream
to the JTAG/OnCE port. It is sampled on the rising edge of TCK and
has an on-chip pull-up resistor.
1
TDO
Output
Tri-stated
Test Data Output
—This tri-statable output pin provides a serial
output data stream from the JTAG/OnCE port. It is driven in the
Shift-IR and Shift-DR controller states, and changes on the falling
edge of TCK.
1
TRST
Input
(Schmitt)
Input, pulled
high internally
Test Reset
—As an input, a low signal on this pin provides a reset
signal to the JTAG TAP controller. To ensure complete hardware
reset, TRST should be asserted at power-up and whenever RESET
is asserted. The only exception occurs in a debugging environment
when a hardware device reset is required and it is necessary not to
reset the OnCE/JTAG module. In this case, assert RESET, but do
not assert TRST.
1
DE
Output
Output
Debug Event
—DE provides a low pulse on recognized debug
events.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56F805ACIM | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Targeting Document for the 56F805 3-Phase AC Induction Motor V/Hz Control |
| DSP56F805BLDCQE | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Targeting Document for the 56F805 BLDC Motor Control Application with Quadrature Encoder |
| DSP56F805D | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:16-bit Hybrid Controller |
| DSP56F805E | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| DSP56F805EVM | 功能描述:開(kāi)發(fā)板和工具包 - 其他處理器 Evaluation Kit For DSP56F805 RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類(lèi)型:I2C, SPI, USB 工作電源電壓: |
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