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參數(shù)資料
| 型號： | DSP56F805 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 16-bit Hybrid Controller(16位混合控制器) |
| 中文描述： | 16位混合控制器（16位混合控制器） |
| 文件頁數(shù)： | 1/48頁 |
| 文件大?。?/td> | 967K |
| 代理商： | DSP56F805 |
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DSP56F805/D
Rev. 12.0
,
02/2004
Motorola, Inc., 2004. All rights reserved.
56F805
Technical Data
56F805 16-bit Hybrid Controller
Up to 40 MIPS at 80MHz core frequency
DSP and MCU functionality in a unified,
C-efficient architecture
Hardware DO and REP loops
MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
31.5K
×
16-bit words Program Flash
512
×
16-bit words Program RAM
4K
×
16-bit words Data Flash
2K
×
16-bit words Data RAM
2K
×
16-bit words Boot Flash
Up to 64K
×
16-bit words each of external
Program and Data memory
Two 6-channel PWM Modules
Two 4-channel, 12-bit ADCs
Two Quadrature Decoders
CAN 2.0 B Module
Two Serial Communication Interfaces (SCIs)
Serial Peripheral Interface (SPI)
Up to four General Purpose Quad Timers
JTAG/OnCE
TM
port for debugging
14 Dedicated and 18 Shared GPIO lines
144-pin LQFP Package
Figure 1. 56F805 Block Diagram
JTAG/
OnCE
Port
Digital Reg
Analog Reg
Low Voltage
Supervisor
Program Controller
and
Hardware Looping Unit
Data ALU
16 x 16 + 36
→
36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Address
Generation
Unit
Bit
Manipulation
Unit
PLL
Clock Gen
16-Bit
56800
Core
PAB
PDB
XDB2
CGDB
XAB1
XAB2
XTAL
EXTAL
INTERRUPT
CONTROLS
IPBB
CONTROLS
IPBus Bridge
(IPBB)
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
COP RESET
RESET
IRQA
IRQB
Application-
Specific
Memory &
Peripherals
Interrupt
Controller
Program Memory
32252 x 16 Flash
512 x 16 SRAM
Boot Flash
2048 x 16 Flash
Data Memory
4096 x 16 Flash
2048 x 16 SRAM
COP/
Watchdog
SPI
or
GPIO
Dedicated
GPIO
*
includes TCS pin which is reserved for factory use and is tied to
VSS
SCI0
or
GPIO
Quad Timer D
/ Alt Func
Quad Timer C
A/D1
A/D2
VREF
ADC
4
2
4
4
4
4
6
PWM Outputs
Fault Inputs
PWMA
16
16
VCAPC
V
DD
V
SS
V
DDA
V
SSA
6
2
8
8*
EXTBOOT
Current Sense Inputs
3
Quadrature
Decoder 0/
Quad Timer A
CAN 2.0A/B
2
CLKO
External
Address Bus
Switch
External
Data Bus
Switch
Bus
Control
External
Bus
Interface
Unit
RD Enable
WR Enable
DS Select
PS Select
10
16
6
A[00:05]
A[06:15] or
GPIO-E2:E3 &
GPIO-A0:A7
D[00:15]
4
4
6
PWM Outputs
Fault Inputs
PWMB
Current Sense Inputs
3
Quadrature
Decoder 1/
Quad B Timer
4
2
SCI1
or
GPIO
2
14
VPP
RSTO
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56F805ACIM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Targeting Document for the 56F805 3-Phase AC Induction Motor V/Hz Control |
| DSP56F805BLDCQE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Targeting Document for the 56F805 BLDC Motor Control Application with Quadrature Encoder |
| DSP56F805D | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:16-bit Hybrid Controller |
| DSP56F805E | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| DSP56F805EVM | 功能描述:開發(fā)板和工具包 - 其他處理器 Evaluation Kit For DSP56F805 RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
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