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參數(shù)資料
| 型號(hào)： | DSF10K |
| 廠商： | Altera Corporation |
| 英文描述： | EMBEDDED PROGRAMMABLE LOGIC FAMILY |
| 中文描述： | 嵌入式可編程邏輯系列 |
| 文件頁(yè)數(shù)： | 5/138頁(yè) |
| 文件大小： | 2116K |
| 代理商： | DSF10K |
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Altera Corporation
5
FLEX 10K Embedded Programmable Logic Family Data Sheet
Notes to tables:
(1)
Contact Altera Customer Marketing for up-to-date information on package availability.
(2)
FLEX 10K and FLEX 10KA device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), pin-grid array (PGA),
and FineLine BGA
packages.
(3)
This option will be supported with a 256-pin FineLine BGA package. By using SameFrame pin migration, all
FineLine BGA packages are pin compatible. For example, a board can be designed to support both 256-pin and
484-pin FineLine BGA packages. The Quartus and MAX+PLUS II software automatically avoids conflicting pins
when future migration is set.
General
Description
Altera’s FLEX 10K devices are the industry’s first embedded PLDs. Based
on reconfigurable CMOS SRAM elements, the Flexible Logic Element
MatriX (FLEX) architecture incorporates all features necessary to
implement common gate array megafunctions. With up to 250,000 gates,
the FLEX 10K family provides the density, speed, and features to integrate
entire systems, including multiple 32-bit buses, into a single device.
FLEX 10K devices are reconfigurable, which allows 100
%
testing prior to
shipment. As a result, the designer is not required to generate test vectors
for fault coverage purposes. Additionally, the designer does not need to
manage inventories of different ASIC designs; FLEX 10K devices can be
configured on the board for the specific functionality required.
Table 6
shows FLEX 10K performance for some common designs. All
performance values were obtained with Synopsys DesignWare or LPM
functions. No special design technique was required to implement the
applications; the designer simply inferred or instantiated a function in a
Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or
schematic design file.
Notes:
(1)
(2)
(3)
The speed grade of this application is limited because of clock high and low specifications.
This application uses combinatorial inputs and outputs.
This application uses registered inputs and outputs.
Table 6. FLEX 10K & FLEX 10KA Performance
Application
Resources
Used
Performance
Units
Speed Grade
LEs
EABs
-1
-2
-3
-4
16-bit loadable
counter
16-bit accumulator
16-to-1 multiplexer
256
×
8 RAM read
cycle speed
256
×
8 RAM write
cycle speed
(1)
16
0
204
166
125
95
MHz
(1)
(2)
16
10
0
0
0
1
204
4.2
172
166
5.8
145
125
6.0
108
95
7.0
84
MHz
ns
MHz
(3)
(3)
0
1
106
89
68
63
MHz
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