參數(shù)資料
型號(hào): DSF10K
廠商: Altera Corporation
英文描述: EMBEDDED PROGRAMMABLE LOGIC FAMILY
中文描述: 嵌入式可編程邏輯系列
文件頁數(shù): 18/138頁
文件大小: 2116K
代理商: DSF10K
18
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
LE Operating Modes
The FLEX 10K LE can operate in the following four modes:
I
I
I
I
Normal mode
Arithmetic mode
Up/down counter mode
Clearable counter mode
Each of these modes uses LE resources differently. In each mode, seven
available inputs to the LE—the four data inputs from the LAB local
interconnect, the feedback from the programmable register, and the
carry-in and cascade-in from the previous LE—are directed to different
destinations to implement the desired logic function. Three inputs to the
LE provide clock, clear, and preset control for the register. Quartus and
MAX+PLUS II software packages, in conjunction with parameterized
functions such as LPM and DesignWare functions, automatically chooses
the appropriate mode for common functions such as counters, adders,
and multipliers. If required, the designer can also create special-purpose
functions which use a specific LE operating mode for optimal
performance.
The architecture provides a synchronous clock enable to the register in all
four modes. Quartus and MAX+PLUS II software packages can set
DATA1
to enable the register synchronously, providing easy implementation of
fully synchronous designs.
Figure 9
shows the LE operating modes.
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