參數(shù)資料
型號(hào)： DS80CH11
廠商： DALLAS SEMICONDUCTOR
元件分類： Microcontroller
英文描述： 8-BIT, MICROCONTROLLER, PQFP128
封裝： TQFP-128
文件頁(yè)數(shù)： 75/88頁(yè)
文件大?。?/td> 598K
代理商： DS80CH11
DS80CH11
011200 77/88
13.3.2 MOVX USING STRETCH MEMORY CYCLES
(0
°C to 70°C; VCC=5.0 ± 10%)
PARAMETER
SYMBOL
VARIABLE CLOCK
UNITS
STRETCH
PARAMETER
SYMBOL
MIN
MAX
UNITS
STRETCH
Data Access ALE Pulse Width
tLHLL2
1.5tCLCL–5
2tCLCL–5
ns
tMCS=0
tMCS>0
Address Hold after ALE Low for
MOVX Write
tLLAX2
0.5tCLCL–5
tCLCL–5
ns
tMCS=0
tMCS>0
RD Pulse Width
tRLRH
2tCLCL–5
tMCS–10
ns
tMCS=0
tMCS>0
WR Pulse Width
tWLWH
2tCLCL–5
tMCS–10
ns
tMCS=0
tMCS>0
RD Low to Valid Data In
tRLDV
2tCLCL–20
tMCS–20
ns
tMCS=0
tMCS>0
Data Hold after Read
tRHDX
0
ns
Data Float after Read
tRHDZ
tCLCL–5
2tCLCL–5
ns
tMCS=0
tMCS>0
ALE Low to Valid Data In
tLLDV
2.5tCLCL–20
tMCS+tCLCL–40
ns
tMCS=0
tMCS>0
Port 0 Address to Valid Data In
tAVDV1
3tCLCL–20
tMCS+1.5tCLCL–20
ns
tMCS=0
tMCS>0
Port 2 Address to Valid Data In
tAVDV2
3.5tCLCL–20
tMCS+2tCLCL–20
ns
tMCS=0
tMCS>0
ALE Low to RD or WR Low
tLLWL
0.5tCLCL–5
tCLCL–5
0.5tCLCL+5
tCLCL+5
ns
tMCS=0
tMCS>0
Port 0 Address to RD or WR Low
tAVWL1
tCLCL–5
2tCLCL–5
ns
tMCS=0
tMCS>0
Port 2 Address to RD or WR Low
tAVWL2
1.5tCLCL–5
2.5tCLCL–5
ns
tMCS=0
tMCS>0
Data Valid to WR Transition
tQVWX
–5
ns
Data Hold after Write
tWHQX
tCLCL–5
2tCLCL–5
ns
tMCS=0
tMCS>0
RD Low to Address Float
tRLAZ
–0.5tCLCL–5
ns
RD or WR High to ALE High
tWHLH
0
tCLCL–5
10
tCLCL+5
ns
tMCS=0
tMCS>0
NOTE:
tMCS is a time period related to the Stretch memory cycle selection. The following table shows the value of tMCS for
each Stretch selection.
M2
M1
M0
MOVX CYCLES
tMCS
0
2 machine cycles
0
1
3 machine cycles (default)
4 tCLCL
0
1
0
4 machine cycles
8 tCLCL
0
1
5 machine cycles
12 tCLCL
1
0
6 machine cycles
16 tCLCL
1
0
1
7 machine cycles
20 tCLCL
1
0
8 machine cycles
24 tCLCL
1
9 machine cycles
28 tCLCL
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