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參數(shù)資料
| 型號(hào)： | DS80CH11 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Microcontroller |
| 英文描述： | 8-BIT, MICROCONTROLLER, PQFP128 |
| 封裝： | TQFP-128 |
| 文件頁(yè)數(shù)： | 66/88頁(yè) |
| 文件大小： | 598K |
| 代理商： | DS80CH11 |
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DS80CH11
011200 69/88
amplifier by setting the XTOFF bit (PMR.3) to a 1. This
can only be done when XT/RG = 0.
When changing the clock source, the selection will take
effect after a one instruction cycle delay. This applies to
changes from crystal to ring and vise versa. However,
this assumes that the crystal amplifier is running. In
most cases, when the ring is active, software previously
disabled the crystal to save power. If ring operation is
being used and the system must switch to crystal opera-
tion, the crystal must first be enabled. Set the XTOFF bit
to a 0. At this time, the crystal oscillation will begin. The
SEM then provides a warm–up delay to make certain
that the frequency is stable. Hardware will set the
XTUP bit (STATUS.4) to a 1 when the crystal is ready for
use. Then software should write XT/RG to a 1 to begin
operating from the crystal. Hardware prevents writing
XT/RG to a 1 before XTUP = 1. The delay between
XTOFF = 0 and XTUP = 1 will be 65,536 crystal clocks.
Switchback has no effect on the clock source. If soft-
ware selects a reduced clock divider and enables the
ring, a Switchback will only restore the divider speed.
The ring will remain as the time base until altered by soft-
ware.
If there is serial activity, Switchback usually
occurs with enough time to create proper baud rates.
This is not true if the crystal is off and the CPU is running
from the ring. If sending a serial character that wakes
the system from crystaless Slow Clock Mode, then it
should be a dummy character of no importance with a
subsequent delay for crystal startup.
The flow chart in Figure 12–1 illustrates a typical deci-
sion set associated with Slow Clock Mode.
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| DS80EP100 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables |
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