參數(shù)資料
型號(hào)： DS80CH11
廠商： DALLAS SEMICONDUCTOR
元件分類： Microcontroller
英文描述： 8-BIT, MICROCONTROLLER, PQFP128
封裝： TQFP-128
文件頁(yè)數(shù)： 27/88頁(yè)
文件大?。?/td> 598K
代理商： DS80CH11
DS80CH11
011200 33/88
6.0
2–WIRE SERIAL INTERFACE
6.1
INTRODUCTION
The SEM provides two industry standard 2–Wire serial
interfaces for processor–processor and processor–
slave bi–directional communication. The major fea-
tures of these buses include:
Only two signal lines are required per bus: a serial
clock line (SCL) and a serial data line (SDA).
Each device connected to the bus is software
addressable by a unique address.
Masters can operate as Master–transmitter or Mas-
ter–receiver.
Multiple master capability via collision detection and
arbitration to prevent data corruption if two or more
masters simultaneously initiate a data transfer.
Serial clock synchronization allows devices with dif-
ferent bit rates to communicate via the same serial
bus.
Devices can be added to or removed from the bus
without affecting any other circuit on the bus.
Both on–chip 2–Wire ports support four modes of
operation: Master transmitter, Master receiver, Slave
transmitter, Slave receiver. Byte–oriented data trans-
port, clock generation, address recognition, and bus
control arbitration are all performed by the hardware.
Double–buffering is provided on receive, allowing a full
word time to service the port during multiple byte data
transfers.
Figure 6–1 is a block diagram which illustrates the hard-
ware of both 2–Wire serial ports. For simplicity “x” rep-
resents 1 for Port 1 and 2 for Port 2.
2–WIRE SERIAL PORT BLOCK DIAGRAM Figure 6–1
ADDRESS
COMPARE
2WSADRx – ADDRESS
REGISTER
2WCONx – CONTROL
REGISTER
2WFSx – FREQUENCY
SELECT
DIVIDE BY
RELOAD VALUE
R/W
09AH
0DAH
R/W
09DH
0D9H
R/W
09CH
0D3H
EN
DIVIDE BY
8 PRESCALE
tMCLK
2WSTAT1x – STATUS
REGISTER
2WSTAT2x – STATUS
REGISTER
EN
R/W
09EH
0DAH
RD
09FH
0DBH
2WDATx – RECEIVE
DATA BUFFER
RD
09BH
0D2H
EN
SHIFT
REGISTER
WR
09BH
0D2H
EN
DOUT
DIN
ACK
TIMING &
CONTROL
LOGIC
MSB
LSB
ARBITRATION
LOGIC
SERIAL
CLOCK GEN.
SDAx
PIN
SCLx
PIN
INTERNAL
DATA BUS
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