參數(shù)資料
型號: DS80CH11
廠商: DALLAS SEMICONDUCTOR
元件分類: Microcontroller
英文描述: 8-BIT, MICROCONTROLLER, PQFP128
封裝: TQFP-128
文件頁數(shù): 74/88頁
文件大?。?/td> 598K
代理商: DS80CH11
DS80CH11
011200 76/88
7. During a 0 to 1 transition, a one–shot drives the ports hard for two oscillator clock cycles. This measurement
reflects port in transition mode. In addition, this specification applies to any of the Port 6.0–Port 6.3 pins when
the associated PWM channel is enabled.
8. Ports 1, 2, and 3 source transition current when being pulled down externally. Current reaches its maximum at
approximately 2V.
9. 0.45<VIN<VCC. Not a high impedance input. This port is a weak address holding latch in Bus Mode. Peak current
occurs near the input transition point of the latch, approximately 2V.
10. 0.45<VIN<VCC. RST=VCC. This condition mimics operation of pins in I/O mode.
13.3 MICROCONTROLLER AC ELECTRICAL
CHARACTERISTICS
13.3.1 EXTERNAL PROGRAM MEMORY
CHARACTERISTICS
(0
°C to 70°C; VCC=5.0 ± 10%)
PARAMETER
SYMBOL
25 MHz
VARIABLE CLOCK
UNITS
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
Oscillator Frequency
1/tCLCL
0
25
0
25
MHz
ALE Pulse Width
tLHLL
55
(3tCLCL/2)–5
ns
Port 0 Address Valid to ALE Low
tAVLL
15
(tCLCL/2)–5
ns
Address Hold after ALE Low
tLLAX1
15
(tCLCL/2)–5
ns
ALE Low to Valid Instruction In
tLLIV
80
2.5tCLCL–20
ns
ALE Low to PSEN Low
tLLPL
15
(tCLCL/2)–5
ns
PSEN Pulse Width
tPLPH
75
2tCLCL–5
ns
PSEN Low to Valid Instruction In
tPLIV
60
2tCLCL–20
ns
Input Instruction Hold after PSEN
tPXIX
0
ns
Input Instruction Float after PSEN
tPXIZ
35
tCLCL–5
ns
Port 0 Address to Valid
Instruction In
tAVIV1
100
3tCLCL–20
ns
Port 2 Address to Valid
Instruction In
tAVIV2
115
3.5tCLCL–25
ns
PSEN Low to Address Float
tPLAZ
0
ns
NOTES:
1. All signals rated over operating temperature.
2. All signals characterized with load capacitance of 80 pF except Port 0, ALE, PSEN, RD and WR with 100 pF.
3. Interfacing to memory devices with float times (turn off times) over 25 ns may cause contention. This will not dam-
age the parts, but will cause an increase in operating current.
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