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參數(shù)資料
| 型號： | DS80CH11 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Microcontroller |
| 英文描述： | 8-BIT, MICROCONTROLLER, PQFP128 |
| 封裝： | TQFP-128 |
| 文件頁數(shù)： | 14/88頁 |
| 文件大?。?/td> | 598K |
| 代理商： | DS80CH11 |
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DS80CH11
011200 21/88
INSTRUCTION SET SUMMARY Table 3–1 (cont’d)
Bit Manipulation
Instructions:
CLR C
1
4
ANL C, bit
2
8
CLR bit
2
8
ANL C, bit
28
SETB C
1
4
ORL C, bit
2
8
SETB bit
2
8
ORL C, bit
28
CPL C
1
4
MOV C, bit
2
8
CPL bit
2
8
MOV bit, C
2
8
Program Branching
Instructions:
ACALL addr 11
2
12
CJNE A, direct, rel
3
16
LCALL addr 16
3
16
CJNE A, #data, rel
3
16
RET
1
16
CJNE Rn, #data, rel
3
16
RETI
1
16
CJNE @ Ri, #data, rel
3
16
AJMP addr 11
2
12
NOP
1
4
LJMP addr 16
3
16
JC rel
2
12
SJMP rel
2
12
JNC rel
2
12
JMP @A+DPTR
1
12
JB bit, rel
3
16
JZ rel
2
12
JNB bit, rel
3
16
JNZ rel
2
12
JBC bit, rel
3
16
DJNZ Rn, rel
2
12
DJNZ direct, rel
3
16
The Table above shows the speed for each class of
instruction. Note that many of the instructions have mul-
tiple opcodes. There are 255 opcodes for 111 instruc-
tions. Of the 255 opcodes, 159 are three times faster
than the original 80C32. While a system than empha-
sizes those instructions will see the most improvement,
the large total number that receive a three to one
improvement assure a dramatic speed increase for any
system. The speed improvement summary is provided
below.
3.3
SPEED IMPROVEMENT
The following table summarizes the speed improve-
ment of the High Speed Micro core over a standard 12
clock / machine cycle 8052 device.
#Opcodes
Speed Improvement
159
3.0 x
51
1.5 x
43
2.0 x
2
2.4 x
255
Average: 2.5
3.4
INSTRUCTION SET ADDITIONAL
REFERENCES
The user should refer to the Dallas High Speed Micro
User’s Guide for a complete description of the instruc-
tion set including its address modes, coding, and timing
for the SEM.
3.5
RESET
The High–Speed Micro has three ways of entering a
reset state:
Power–On / Fail Reset
Watchdog Timer Reset
External Reset
The operation of the CPU timing and states during a
reset are documented in the Dallas High Speed Micro
User’s Guide under the “Reset Conditions” section. The
Watchdog Timer reset is documented in the Watchdog
Timer section of the Dallas High Speed Micro User’s
Guide. The operation of the Power–On / Fail reset is
described in the Power Management section of this doc-
ument.
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| DS87C520-MCL | 8-BIT, OTPROM, MICROCONTROLLER, PDIP40 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS80CH11+E02 | 制造商:Maxim from Components Direct 功能描述:MAXIM DS80CH11+E02 SYSTEM ENERGY MANAGERS - Trays 制造商:Maxim 功能描述:Maxim DS80CH11+E02 System Energy Managers |
| DS80CH11-E02 | 制造商:Maxim from Components Direct 功能描述:MAXIM DS80CH11-E02 SYSTEM ENERGY MANAGERS - Trays 制造商:Maxim 功能描述:Maxim DS80CH11-E02 System Energy Managers |
| DS80E100 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables |
| DS80EP100 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables |
| DS80EP100_08 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables |
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