參數(shù)資料
型號: DEMO9RS08KA2
廠商: Freescale Semiconductor
文件頁數(shù): 22/136頁
文件大?。?/td> 0K
描述: DEMO BOARD FOR 9RS08KA2
產(chǎn)品培訓模塊: Mechatronics
USBSpyder08 Discovery Kit
RS08KA2 Low-End Microcontroller Series
MC9RS08KA8 Microcontroller
標準包裝: 1
系列: RS08
類型: MCU
適用于相關產(chǎn)品: MC9RS08KA2
所含物品: 板,線纜,CD,文檔,樣品 IC
產(chǎn)品目錄頁面: 730 (CN2011-ZH PDF)
相關產(chǎn)品: MC9RS08KA2CSCRTR-ND - IC MCU 8BIT 2K FLASH 8-SOIC
PC9RS08KA2PAE-ND - MCU 8BIT 2KB FLASH RS08 8-DIP
PC9RS08KA2FPE-ND - MCU 8BIT 2KB FLASH RS08 6-VDFN
PC9RS08KA2DWE-ND - MCU 8BIT 2KB FLASH RS08 8-SOIC
MC9RS08KA2CPC-ND - IC MCU 8-BIT 2K FLASH 8-PDIP
MC9RS08KA2CDB-ND - IC MCU 8-BIT 2K FLASH 6-DFN
MC9RS08KA2CSC-ND - IC MCU 8-BIT 2K FLASH 8-SOIC
Appendix A Electrical Characteristics
MC9RS08KA2 Series Data Sheet, Rev. 4
118
Freescale Semiconductor
A.9
AC Characteristics
This section describes ac timing characteristics for each peripheral system.
A.9.1
Control Timing
Figure A-1. Reset Timing
Stop recovery time (FLL wakeup to previous acquired
frequency)
IREFSTEN=0
IREFSTEN=1
t_wakeup
tir_wu
tfll_wu
—100
86
μs
1 Data in typical column was characterized at 3.0 V and 5.0 V, 25
°C or is typical recommended value.
2 This parameter is characterized and not tested on each device.
3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (FBILP) to FLL enabled (FEI, FBI).
Table A-8. Control Timing
Parameter
Symbol
Min
Typical
Max
Unit
Bus frequency (tcyc = 1/fBus)fBus
dc
10
MHz
Real time interrupt internal oscillator period
tRTI
700
1000
1300
μs
External RESET pulse width1
1 This is the shortest pulse that is guaranteed to pass through the pin input filter circuitry. Shorter pulses may or may not be
recognized.
textrst
150
ns
KBI pulse width2
2 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
tKBIPW
1.5 tcyc
——
ns
KBI pulse width in stop1
tKBIPWS
100
ns
Port rise and fall time (load = 50 pF)3
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
3 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40°C to 85°C.
tRise, tFall
11
35
ns
Table A-7. Internal Clock Source Specifications
Characteristic
Symbol
Min
Typ1
Max
Unit
textrst
RESET
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