參數(shù)資料
型號(hào)： CYV15G0404RB
廠商： Cypress Semiconductor Corp.
英文描述： Independent Clock Quad HOTLink II Reclocking Deserializer(獨(dú)立時(shí)鐘，四路HOTLink II時(shí)鐘恢復(fù)串并轉(zhuǎn)換器)
中文描述： 獨(dú)立時(shí)鐘四的HOTLink第二時(shí)鐘重計(jì)解串器（獨(dú)立時(shí)鐘，四路的HOTLink第二時(shí)鐘恢復(fù)串并轉(zhuǎn)換器）
文件頁(yè)數(shù)： 9/26頁(yè)
文件大?。?/td> 542K
代理商： CYV15G0404RB
CYV15G0404RB
Document #: 38-02102 Rev. *B
Page 9 of 26
LDTDEN
LVTTL Input,
internal pull-up
Level Detect Transition Density Enable
. When LDTDEN is HIGH, the Signal
Level Detector, Range Controller, and Transition Density Detector are all enabled
to determine if the RXPLL tracks TRGCLKx± or the selected input serial data
stream. If the Signal Level Detector, Range Controller, or Transition Density
Detector are out of their respective limits while LDTDEN is HIGH, the RXPLL locks
to TRGCLKx± until such a time they become valid. The SDASEL[A..D][1:0] inputs
are used to configure the trip level of the Signal Level Detector. The Transition
Density Detector limit is one transition in every 60 consecutive bits. When
LDTDEN is LOW, only the Range Controller is used to determine if the RXPLL
tracks TRGCLKx± or the selected input serial data stream. It is recommended to
set LDTDEN = HIGH.
Use Local Clock
. When ULCx is LOW, the RXPLL is forced to lock to TRGCLKx±
instead of the received serial data stream. While ULCx is LOW, the LFIx for the
associated channel is LOW indicating a link fault.
When ULCx is HIGH, the RXPLL performs Clock and Data Recovery functions on
the input data streams. This function is used in applications in which a stable
RXCLKx± is needed. In cases when there is an absence of valid data transitions
for a long period of time, or the high-gain differential serial inputs (INx±) are left
floating, there may be brief frequency excursions of the RXCLKx± outputs from
TRGCLKx±.
Serial Rate Select
. The SPDSELx inputs specify the operating signaling-rate
range of each channel’s receive PLL.
LOW = 195 – 400 MBd
MID = 400 – 800 MBd
HIGH = 800 – 1500 MBd.
Receive Input Selector
. The INSELx input determines which external serial bit
stream is passed to the receiver’s Clock and Data Recovery circuit. When INSELx
is HIGH, the Primary Differential Serial Data Input, INx1±, is selected for the
associated receive channel. When INSELx is LOW, the Secondary Differential
Serial Data Input, INx2±, is selected for the associated receive channel.
Link Fault Indication Output
. LFIx is an output status indicator signal. LFIx is the
logical OR of six internal conditions. LFIx is asserted LOW when any of the
following conditions is true:
Received serial data rate outside expected range
Analog amplitude below expected levels
Transition density lower than expected
Receive channel disabled
ULCx is LOW
Absence of TRGCLKx±.
ULCA
ULCB
ULCC
ULCD
LVTTL Input,
internal pull-up
SPDSELA
SPDSELB
SPDSELC
SPDSELD
3-Level Select
[2]
static control input
INSELA
INSELB
INSELC
INSELD
LVTTL Input,
asynchronous
LFIA
LFIB
LFIC
LFID
LVTTL Output,
asynchronous
Device Configuration and Control Bus Signals
WREN
LVTTL input,
asynchronous,
internal pull-up
ADDR[3:0]
LVTTL input
asynchronous,
internal pull-up
Control Write Enable
. The WREN input writes the values of the DATA[7:0] bus
into the latch specified by the address location on the ADDR[3:0] bus.
[3]
Control Addressing Bus
. The ADDR[3:0] bus is the input address bus used to
configure the device. The WREN input writes the values of the DATA[7:0] bus into
the latch specified by the address location on the ADDR[3:0] bus.
[3]
Table 3
lists
the configuration latches within the device, and the initialization value of the
latches upon the assertion of RESET.
Table 4
shows how the latches are mapped
in the device.
Notes:
2.
3-Level Select inputs are used for static configuration. These are ternary inputs that make use of logic levels of LOW, MID, and HIGH. The LOW level is usually
implemented by direct connection to V
(ground). The HIGH level is usually implemented by direct connection to V
CC
(power). The MID level is usually
implemented by not connecting the input (left floating), which allows it to self bias to the proper level.
See
Device Configuration and Control Interface
for detailed information on the operation of the Configuration Interface.
3.
Pin Definitions
(continued)
CYV15G0404RB Quad HOTLink II Deserializing Reclocker
Name
I/O Characteristics
Signal Description
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