- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379101 > CYV15G0404RB (Cypress Semiconductor Corp.) Independent Clock Quad HOTLink II Reclocking Deserializer(獨(dú)立時(shí)鐘，四路HOTLink II時(shí)鐘恢復(fù)串并轉(zhuǎn)換器) PDF資料下載
參數(shù)資料
| 型號(hào)： | CYV15G0404RB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock Quad HOTLink II Reclocking Deserializer(獨(dú)立時(shí)鐘，四路HOTLink II時(shí)鐘恢復(fù)串并轉(zhuǎn)換器) |
| 中文描述： | 獨(dú)立時(shí)鐘四的HOTLink第二時(shí)鐘重計(jì)解串器（獨(dú)立時(shí)鐘，四路的HOTLink第二時(shí)鐘恢復(fù)串并轉(zhuǎn)換器） |
| 文件頁數(shù)： | 14/26頁 |
| 文件大?。?/td> | 542K |
| 代理商： | CYV15G0404RB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁
CYV15G0404RB
Document #: 38-02102 Rev. *B
Page 14 of 26
8, and 11) are the dynamic control latches that are associated
with enabling dynamic functions within the device.
Latch Bank 14 is also useful for those users that do not need
the latch-based programmable feature of the device. This
latch bank could be used in those applications that do not need
to modify the default value of the static latch banks, and that
can afford a global (i.e., not independent) control of the
dynamic signals. In this case, this feature becomes available
when ADDR[3:0] is left unchanged with a value of “1110” and
WREN is left asserted. The signals present in DATA[7:0] effec-
tively become global control pins, and for the latch banks 2, 5,
8 and 11.
Static Latch Values
There are some latches in the table that have a static value (ie.
1, 0, or X). The latches that have a ‘1’ or ‘0’ must be configured
with their corresponding value each time that their associated
latch bank is configured. The latches that have an ‘X’ are don’t
cares and can be configured with any value
Table 3. Device Configuration and Control Latch Descriptions
Name
RXRATEA
RXRATEB
RXRATEC
RXRATED
Signal Description
Receive Clock Rate Select
. The initialization value of the RXRATEx latch = 1. RXRATEx is used to select
the rate of the RXCLKx± clock output.
When RXRATEx = 1, the RXCLKx± clock outputs are complementary clocks that follow the recovered
clock operating at half the character rate. Data for the associated receive channels should be latched
alternately on the rising edge of RXCLKx+ and RXCLKx–.
When RXRATEx = 0, the RXCLKx± clock outputs are complementary clocks that follow the recovered
clock operating at the character rate. Data for the associated receive channels should be latched on the
rising edge of RXCLKx+ or falling edge of RXCLKx–.
Primary Serial Data Input Signal Detector Amplitude Select
. The initialization value of the
SDASEL1x[1:0] latch = 10. SDASEL1x[1:0] selects the trip point for the detection of a valid signal for the
INx1± Primary Differential Serial Data Inputs.
When SDASEL1x[1:0] = 00, the Analog Signal Detector is disabled.
When SDASEL1x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV.
When SDASEL1x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV.
When SDASEL1x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV.
Secondary Serial Data Input Signal Detector Amplitude Select
. The initialization value of the
SDASEL2x[1:0] latch = 10. SDASEL2x[1:0] selects the trip point for the detection of a valid signal for the
INx2± Secondary Differential Serial Data Inputs.
When SDASEL2x[1:0] = 00, the Analog Signal Detector is disabled
When SDASEL2x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV.
When SDASEL2x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV.
When SDASEL2x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV.
Training Clock Rate Select
. The initialization value of the TRGRATEx latch = 0. TRGRATEx is used to
select the clock multiplier for the training clock input to the associated CDR PLL. When TRGRATEx = 0,
the associated TRGCLKx± input is not multiplied before it is passed to the CDR PLL. When TRGRATEx
= 1, the TRGCLKx± input is multiplied by 2 before it is passed to the CDR PLL. TRGRATEx = 1 and
SPDSELx = LOW is an invalid state and this combination is reserved.
Receive Channel Enable
. The initialization value of the RXPLLPDx latch = 0. RXPLLPDx selects if the
associated receive channel is enabled or powered-down. When RXPLLPDx = 0, the associated receive
PLL and analog circuitry are powered-down. When RXPLLPDx = 1, the associated receive PLL and
analog circuitry are enabled.
Receive Bist Disable / SMPTE Receive Enable
. The initialization value of the RXBISTx[1:0] latch = 11.
For SMPTE data reception, RXBISTx[1:0] should not remain in this initialization state (11). RXBISTx[1:0]
selects if receive BIST is disabled or enabled and sets the associated channel for SMPTE data reception.
When RXBISTx[1:0] = 01, the receiver BIST function is disabled and the associated channel is set to
receive SMPTE data. When RXBISTx[1:0] = 10, the receive BIST function is enabled and the associated
channel is set to receive BIST data. RXBISTx[1:0] = 00 and RXBISTx[1:0] = 11 are invalid states.
Reclocker Secondary Differential Serial Data Output Driver Enable
. The initialization value of the
ROE2x latch = 0. ROE2x selects if the ROUT2± secondary differential output drivers are enabled or
disabled. When ROE2x = 1, the associated serial data output driver is enabled allowing data to be
transmitted from the transmit shifter. When ROE2x = 0, the associated serial data output driver is disabled.
When a driver is disabled via the configuration interface, it is internally powered down to reduce device
power. If both serial drivers for a channel are in this disabled state, the associated internal logic for that
channel is also powered down. A device reset (RESET sampled LOW) disables all output drivers.
SDASEL1A[1:0]
SDASEL1B[1:0]
SDASEL1C[1:0]
SDASEL1D[1:0]
SDASEL2A[1:0]
SDASEL2B[1:0]
SDASEL2C[1:0]
SDASEL2D[1:0]
TRGRATEA
TRGRATEB
TRGRATEC
TRGRATED
RXPLLPDA
RXPLLPDB
RXPLLPDC
RXPLLPDD
RXBISTA[1:0]
RXBISTB[1:0]
RXBISTC[1:0]
RXBISTD[1:0]
ROE2A
ROE2B
ROE2C
ROE2D
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYV270M0101EQ | Adaptive Video Cable Equalizer (SOIC) |
| CYV270M0101EQ-SXC | Adaptive Video Cable Equalizer (SOIC) |
| CYW2338 | Dual Serial Input PLL with 2.5- and 1.1-GHz Prescalers |
| CYWM6935PAEC | WirelessUSB⑩ LR+PA Radio Module |
| CYWUSB6953-48LFC | WirelessUSB PRoC Flash Programmable MCU + Radio |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYV15G0404RB_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Deserializing Reclocker |
| CYV15G0404RB-BGC | 功能描述:電信線路管理 IC 4x Indep Reclockers COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0404RB-BGXC | 功能描述:視頻 IC 4x Indep Reclockers COM RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CYV270101EQ-SXC | 制造商:Cypress Semiconductor 功能描述: |
| CYV270M0101EQ | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Adaptive Video Cable Equalizer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。