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參數(shù)資料
| 型號(hào)： | CYV15G0404RB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock Quad HOTLink II Reclocking Deserializer(獨(dú)立時(shí)鐘，四路HOTLink II時(shí)鐘恢復(fù)串并轉(zhuǎn)換器) |
| 中文描述： | 獨(dú)立時(shí)鐘四的HOTLink第二時(shí)鐘重計(jì)解串器（獨(dú)立時(shí)鐘，四路的HOTLink第二時(shí)鐘恢復(fù)串并轉(zhuǎn)換器） |
| 文件頁數(shù)： | 13/26頁 |
| 文件大?。?/td> | 542K |
| 代理商： | CYV15G0404RB |
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CYV15G0404RB
Document #: 38-02102 Rev. *B
Page 13 of 26
deserializer with each character generated by the LFSR and
indicates compare errors and BIST status at the RXDx[1:0]
and BISTSTx bits of the Output Register.
The BIST status bus {BISTSTx, RXDx[0], RXDx[1]} indicates
010b or 100b for one character period per BIST loop to
indicate loop completion. This status can be used to check test
pattern progress.
The specific status reported by the BIST state machine is listed
in
Table 5
. These same codes are reported on the receive
status outputs.
If the number of invalid characters received ever exceeds the
number of valid characters by 16, the receive BIST state
machine aborts the compare operations and resets the LFSR
to look for the start of the BIST sequence again.
A device reset (RESET sampled LOW) presets the BIST
Enable Latches to disable BIST on all channels.
BIST Status State Machine
When a receive path is enabled to look for and compare the
received data stream with the BIST pattern, the {BISTSTx,
RXDx[0], RXDx[1]} bits identify the present state of the BIST
compare operation.
The BIST state machine has multiple states, as shown in
Figure 2
and
Table 5
. When the receive PLL detects an out-of-
lock condition, the BIST state is forced to the Start-of-BIST
state, regardless of the present state of the BIST state
machine. If the number of detected errors ever exceeds the
number of valid matches by greater than 16, the state machine
is forced to the WAIT_FOR_BIST state where it monitors the
receive path for the first character of the next BIST sequence.
Power Control
The CYV15G0404RB supports user control of the powered up
or down state of each transmit and receive channel. The
receive channels are controlled by the RXPLLPDx latch via the
device configuration interface. When RXPLLPDx = 0, the
associated PLL and analog circuitry of the channel is disabled.
The transmit channels are controlled by the OE1x and the
OE2x latches via the device configuration interface. The
reclocker function is controlled by the ROE1x and the ROE2x
latches via the device configuration interface. When a driver is
disabled via the configuration interface, it is internally powered
down to reduce device power. If both serial drivers for a
channel are in this disabled state, the associated internal logic
for that channel is also powered down. When the reclocker
serial drivers are disabled, the reclocker function will be
disabled, but the deserialization logic and parallel outputs will
remain enabled.
Device Reset State
When the CYV15G0404RB is reset by assertion of RESET, all
state machines, counters, and configuration latches in the
device are initialized to a reset state. See
Table 3
for the
initialize values of the configuration latches.
Following a device reset, it is necessary to enable the receive
channels used for normal operation. This can be done by
sequencing the appropriate values on the device configuration
interface.
[3]
Device Configuration and Control Interface
The CYV15G0404RB is highly configurable via the configu-
ration interface. The configuration interface allows the device
to be configured globally or allows each channel to be
configured independently.
Table 3
lists the configuration
latches within the device including the initialization value of the
latches upon the assertion of RESET.
Table 4
shows how the
latches are mapped in the device. Each row in the
Table 4
maps to a 8-bit latch bank. There are 16 such write-only latch
banks. When WREN = 0, the logic value in the DATA[7:0] is
latched to the latch bank specified by the values in ADDR[3:0].
The second column of
Table 4
specifies the channels
associated with the corresponding latch bank. For example,
the first three latch banks (0,1 and 2) consist of configuration
bits for channel A. The latch banks 12, 13 and 14 consist of
Global configuration bits and the last latch bank (15) is the
Mask latch bank that can be configured to perform bit-by-bit
configuration.
Global Enable Function
The global enable function, controlled by the GLENx bits, is a
feature that can be used to reduce the number of write opera-
tions needed to setup the latch banks. This function is
beneficial in systems that use a common configuration in
multiple channels. The GLENx bit is present in bit 0 of latch
banks 0 through 11 only. Its default value (1) enables the global
update of the latch bank's contents. Setting the GLENx bit to
0 disables this functionality.
Latch Banks 12, 13, and 14 are used to load values in the
related latch banks in a global manner. A write operation to
latch bank 12 could do a global write to latch banks 0, 3, 6, and
9 depending on the value of GLENx in these latch banks; latch
bank 13 could do a global write to latch banks 1, 4, 7 and 10;
and latch banks 14 could do a global write to latch banks 2, 5,
8 and 11. The GLENx bit cannot be modified by a global write
operation.
Force Global Enable Function
FGLENx forces the global update of the target latch banks, but
does not change the contents of the GLENx bits. If FGLENx =
1 for the associated global channel, FGLENx forces the global
update of the target latch banks.
Mask Function
An additional latch bank (15) is used as a global mask vector
to control the update of the configuration latch banks on a bit-
by-bit basis. A logic 1 in a bit location allows for the update of
that same location of the target latch bank(s), whereas a logic
0 disables it. The reset value of this latch bank is FFh, thereby
making its use optional by default. The mask latch bank is not
maskable. The FGLEN functionality is not affected by the bit 0
value of the mask latch bank.
Latch Types
There are two types of latch banks: static (S) and dynamic (D).
Each channel is configured by 2 static and 1 dynamic latch
banks. The S type contain those settings that normally do not
change for a given application, whereas the D type controls
the settings that could change during the application's lifetime.
The first and second rows of each channel (address numbers
0, 1, 3, 4, 6, 7, 9, and 10) are the static control latches. The
third row of latches for each channel (address numbers 2, 5,
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