參數(shù)資料
型號: CYV15G0404RB
廠商: Cypress Semiconductor Corp.
英文描述: Independent Clock Quad HOTLink II Reclocking Deserializer(獨立時鐘,四路HOTLink II時鐘恢復串并轉(zhuǎn)換器)
中文描述: 獨立時鐘四的HOTLink第二時鐘重計解串器(獨立時鐘,四路的HOTLink第二時鐘恢復串并轉(zhuǎn)換器)
文件頁數(shù): 19/26頁
文件大小: 542K
代理商: CYV15G0404RB
CYV15G0404RB
Document #: 38-02102 Rev. *B
Page 19 of 26
AC Test Loads and Waveforms
CYV15G0404RB AC Electrical Characteristics
V
ODIF
Output Differential Voltage
|(OUT+)
(OUT
)|
100
differential load
150
differential load
450
560
900
1000
mV
mV
Differential Serial Line Receiver Inputs: INA1
±
, INA2
±
, INB1
±
, INB2
±
, INC1
±
, INC2
±
, IND1
±
, IND2
±
V
DIFFs[7]
Input Differential Voltage |(IN+)
(IN
)|
V
IHE
Highest Input HIGH Voltage
V
ILE
Lowest Input LOW Voltage
I
IHE
Input HIGH Current
I
ILE
Input LOW Current
VI
COM[9]
Common Mode input range
100
1200
V
CC
mV
V
V
μ
A
μ
A
V
V
CC
– 2.0
V
IN
= V
IHE
Max.
V
IN
= V
ILE
Min.
((V
CC
– 2.0V)+0.5)min,
(V
CC
– 0.5V) max.
1350
–700
+1.25
+3.1
Power Supply
I
CC [10,11]
Typ.
910
Max.
1270
1320
1270
1320
Max Power Supply Current
TRGCLKx =
MAX
Commercial
Industrial
Commercial
Industrial
mA
mA
mA
mA
I
CC [10,11]
Typical Power Supply Current
TRGCLKx =
125 MHz
900
CYV15G0404RB DC Electrical Characteristics
(continued)
Parameter
Description
Test Conditions
Min.
Max.
Unit
2.0V
0.8V
GND
2.0V
0.8V
80%
20%
80%
20%
R
L
(Includes fixture and
probe capacitance)
3.0V
V
th
= 1.4V
270 ps
270 ps
[13]
V
th
= 1.4V
3.3V
R1
R2
R1 = 590
R2 = 435
C
L
7 pF
(Includes fixture and
probe capacitance)
(a) LVTTL Output Test Load
R
L
= 100
(b) CML Output Test Load
C
L
(c) LVTTL Input Test Waveform
(d) CML/LVPECL Input Test Waveform
1 ns
1 ns
V
IHE
V
ILE
V
IHE
V
ILE
[12]
[12]
Parameter
CYV15G0404RB Receiver LVTTL Switching Characteristics
Over the Operating Range
f
RS
RXCLKx± Clock Output Frequency
t
RXCLKP
RXCLKx± Period = 1/f
RS
t
RXCLKD
RXCLKx± Duty Cycle Centered at 50% (Full Rate and Half Rate)
t
RXCLKR [14]
RXCLKx± Rise Time
t
RXCLKF [14]
RXCLKx± Fall Time
Notes:
9.
The common mode range defines the allowable range of INPUT+ and INPUT
when INPUT+ = INPUT
. This marks the zero-crossing between the true and
complement inputs as the signal switches between a logic-1 and a logic-0.
10. Maximum I
is measured with V
CC
= MAX, T
A
= 25°C, with all channels and Serial Line Drivers enabled, sending a continuous alternating 01 pattern, and
outputs unloaded.
11.
Typical I
is measured under similar conditions except with V
= 3.3V, T
= 25°C, with all channels enabled and one Serial Line Driver per transmit channel
sending a continuous alternating 01 pattern. The redundant outputs on each channel are powered down and the parallel outputs are unloaded.
12. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
13. The LVTTL switching threshold is 1.4V. All timing references are made relative to where the signal edges cross the threshold voltage.
14. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
Description
Min.
Max
Unit
9.75
6.66
–1.0
0.3
0.3
150
102.56
+1.0
1.2
1.2
MHz
ns
ns
ns
ns
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