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參數(shù)資料
| 型號(hào)： | CYV15G0404RB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock Quad HOTLink II Reclocking Deserializer(獨(dú)立時(shí)鐘，四路HOTLink II時(shí)鐘恢復(fù)串并轉(zhuǎn)換器) |
| 中文描述： | 獨(dú)立時(shí)鐘四的HOTLink第二時(shí)鐘重計(jì)解串器（獨(dú)立時(shí)鐘，四路的HOTLink第二時(shí)鐘恢復(fù)串并轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 20/26頁(yè) |
| 文件大?。?/td> | 542K |
| 代理商： | CYV15G0404RB |
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CYV15G0404RB
Document #: 38-02102 Rev. *B
Page 20 of 26
t
RXDv–[18]
Status and Data Valid Time to RXCLKx± (RXRATEx = 0) (Full Rate)
Status and Data Valid Time to RXCLKx± (RXRATEx = 1) (Half Rate)
Status and Data Valid Time to RXCLKx± (RXRATEx = 0)
Status and Data Valid Time to RXCLKx± (RXRATEx = 1)
RECLKOx Clock Frequency
RECLKOx Period=1/f
ROS
RECLKOx Duty Cycle centered at 60% HIGH time
CYV15G0404RB TRGCLKx Switching Characteristics
Over the Operating Range
f
TRG
TRGCLKx Clock Frequency
TRGCLKx Period = 1/f
REF
t
TRGH
TRGCLKx HIGH Time (TRGRATEx = 1)(Half Rate)
TRGCLKx HIGH Time (TRGRATEx = 0)(Full Rate)
t
TRGL
TRGCLKx LOW Time (TRGRATEx = 1)(Half Rate)
TRGCLKx LOW Time (TRGRATEx = 0)(Full Rate)
t
TRGD[20]
TRGCLKx Duty Cycle
t
TRGR[14, 15, 16, 17]
TRGCLKx Rise Time (20%–80%)
t
TRGF[14, 15, 16, 17]
TRGCLKx Fall Time (20%–80%)
t
TRGRX[21]
TRGCLKx Frequency Referenced to Received Clock Frequency
CYV15G0404RB Bus Configuration Write Timing Characteristics
Over the Operating Range
t
DATAH
Bus Configuration Data Hold
t
DATAS
Bus Configuration Data Setup
t
WRENP
Bus Configuration WREN Pulse Width
CYV15G0404RB JTAG Test Clock Characteristics
Over the Operating Range
f
TCLK
JTAG Test Clock Frequency
t
TCLK
JTAG Test Clock Period
CYV15G0404RB Device RESET Characteristics
Over the Operating Range
t
RST
Device RESET Pulse Width
CYV15G0404RB Reclocker Serial Output Characteristics
Over the Operating Range
Parameter
Description
t
B
Bit Time
t
RISE[14]
CML Output Rise Time 20
80% (CML Test Load)
5UI–2.0
[19]
5UI–1.3
[19]
5UI–1.8
[19]
5UI–2.6
[19]
19.5
6.66
–1.9
ns
ns
ns
ns
MHz
ns
ns
t
RXDv+[18]
f
ROS
t
RECLKO
t
RECLKOD
150
51.28
0
19.5
6.6
5.9
2.9
[14]
5.9
2.9
[14]
30
150
51.28
MHz
ns
ns
ns
ns
ns
%
ns
ns
%
TRGCLK
70
2
2
–0.15
+0.15
0
10
10
ns
ns
ns
20
MHz
ns
50
30
ns
Condition
Min.
5128
50
100
180
50
100
180
Max.
660
270
500
1000
270
500
1000
Unit
ps
ps
ps
ps
ps
ps
ps
SPDSELx = HIGH
SPDSELx = MID
SPDSELx =LOW
SPDSELx = HIGH
SPDSELx = MID
SPDSELx =LOW
t
FALL[14]
CML Output Fall Time 80
20% (CML Test Load)
Notes:
15. The ratio of rise time to falling time must not vary by greater than 2:1.
16. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.
17. All transmit AC timing parameters measured with 1ns typical rise time and fall time.
18. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.
19. Receiver UI (Unit Interval) is calculated as 1/(f
*20) (when TRGRATEx = 1) or 1/(f
TRG
* 10) (when TRGRATEx = 0). In an operating link this is equivalent to t
B
.
20. The duty cycle specification is a simultaneous condition with the t
REFH
and t
REFL
cycle cannot be as large as 30%–70%.
21. TRGCLKx± has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time.
TRGCLKx± must be within
±
1500 PPM (
±
0.15%) of the transmitter PLL reference (REFCLKx±) frequency. Although transmitting to a HOTLink II receiver channel
necessitates the frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be
within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard.
CYV15G0404RB AC Electrical Characteristics
(continued)
Parameter
Description
Min.
Max
Unit
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