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參數(shù)資料
| 型號： | CYV15G0404RB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock Quad HOTLink II Reclocking Deserializer(獨立時鐘，四路HOTLink II時鐘恢復(fù)串并轉(zhuǎn)換器) |
| 中文描述： | 獨立時鐘四的HOTLink第二時鐘重計解串器（獨立時鐘，四路的HOTLink第二時鐘恢復(fù)串并轉(zhuǎn)換器） |
| 文件頁數(shù)： | 10/26頁 |
| 文件大?。?/td> | 542K |
| 代理商： | CYV15G0404RB |
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CYV15G0404RB
Document #: 38-02102 Rev. *B
Page 10 of 26
DATA[7:0]
LVTTL input
asynchronous,
internal pull-up
Control Data Bus
. The DATA[7:0] bus is the input data bus used to configure the
device. The WREN input writes the values of the DATA[7:0] bus into the latch
specified by address location on the ADDR[3:0] bus.
[3 ]
Table 3
lists the configu-
ration latches within the device, and the initialization value of the latches upon the
assertion of RESET.
Table 4
shows how the latches are mapped in the device.
Internal Device Configuration Latches
RXRATE[A..D]
SDASEL[2..1][A..D]
[1:0]
RXPLLPD[A..D]
RXBIST[A..D][1:0]
ROE2[A..D]
ROE1[A..D]
GLEN[11..0]
FGLEN[2..0]
Factory Test Modes
SCANEN2
Internal Latch
[4]
Internal Latch
[4]
Receive Clock Rate Select
.
Signal Detect Amplitude Select
.
Internal Latch
[4]
Internal Latch
[4]
Internal Latch
[4]
Internal Latch
[4]
Internal Latch
[4]
Internal Latch
[4]
Receive Channel Power Control
.
Receive Bist Disabled
.
Reclocker Differential Serial Output Driver 2 Enable
.
Reclocker Differential Serial Output Driver 1 Enable
.
Global Latch Enable
.
Force Global Latch Enable
.
LVTTL input,
internal pull-down
LVTTL input,
internal pull-down
Factory Test 2.
SCANEN2 input is for factory testing only. This input may be left
as a NO CONNECT, or GND only.
Factory Test 3
. TMEN3 input is for factory testing only. This input may be left as
a NO CONNECT, or GND only.
TMEN3
Analog I/O
ROUTA1±
ROUTB1±
ROUTC1±
ROUTD1±
ROUTA2±
ROUTB2±
ROUTC2±
ROUTD2±
INA1±
INB1±
INC1±
IND1±
INA2±
INB2±
INC2±
IND2±
JTAG Interface
TMS
CML Differential
Output
Primary Differential Serial Data Output
. The ROUTx1± PECL-compatible CML
outputs (+3.3V referenced) are capable of driving terminated transmission lines or
standard fiber-optic transmitter modules, and must be AC-coupled for PECL-
compatible connections.
Secondary Differential Serial Data Output
. The ROUTx2± PECL-compatible CML
outputs (+3.3V referenced) are capable of driving terminated transmission lines or
standard fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible
connections.
Primary Differential Serial Data Input
. The INx1± input accepts the serial data
stream for deserialization. The INx1± serial stream is passed to the receive CDR
circuit to extract the data content when INSELx = HIGH.
CML Differential
Output
Differential Input
Differential Input
Secondary Differential Serial Data Input
. The INx2± input accepts the serial
data stream for deserialization. The INx2± serial stream is passed to the receiver
CDR circuit to extract the data content when INSELx = LOW.
LVTTL Input,
internal pull-up
LVTTL Input,
internal pull-down
3-State LVTTL Output
Test Mode Select
. Used to control access to the JTAG Test Modes. If maintained
high for
≥
5 TCLK cycles, the JTAG test controller is reset.
JTAG Test Clock
.
TCLK
TDO
Test Data Out
. JTAG data output buffer. High-Z while JTAG test mode is not
selected.
Test Data In
. JTAG data input port.
TDI
LVTTL Input,
internal pull-up
LVTTL Input,
internal pull-up
TRST
JTAG reset signal
. When asserted (LOW), this input asynchronously resets the
JTAG test access port controller.
Note:
4.
See
Device Configuration and Control Interface
for detailed information on the internal latches.
Pin Definitions
(continued)
CYV15G0404RB Quad HOTLink II Deserializing Reclocker
Name
I/O Characteristics
Signal Description
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