參數(shù)資料
型號(hào): CYV15G0404RB
廠商: Cypress Semiconductor Corp.
英文描述: Independent Clock Quad HOTLink II Reclocking Deserializer(獨(dú)立時(shí)鐘,四路HOTLink II時(shí)鐘恢復(fù)串并轉(zhuǎn)換器)
中文描述: 獨(dú)立時(shí)鐘四的HOTLink第二時(shí)鐘重計(jì)解串器(獨(dú)立時(shí)鐘,四路的HOTLink第二時(shí)鐘恢復(fù)串并轉(zhuǎn)換器)
文件頁(yè)數(shù): 16/26頁(yè)
文件大?。?/td> 542K
代理商: CYV15G0404RB
CYV15G0404RB
Document #: 38-02102 Rev. *B
Page 16 of 26
JTAG Support
The CYV15G0404RB contains a JTAG port to allow system
level diagnosis of device interconnect. Of the available JTAG
modes, boundary scan, and bypass are supported. This
capability is present only on the LVTTL inputs and outputs and
the TRGCLKx± clock input. The high-speed serial inputs and
outputs are not part of the JTAG test chain.
3-Level Select Inputs
Each 3-Level select inputs reports as two bits in the scan
register. These bits report the LOW, MID, and HIGH state of
the associated input as 00, 10, and 11 respectively
JTAG ID
The JTAG device ID for the CYV15G0404RB is ‘0C811069’x.
Table 5. Receive BIST Status Bits
{BISTSTx, RXDx[0],
RXDx[1]}
000, 001
010
011
100
101
Description
Receive BIST Status
(Receive BIST = Enabled)
BIST Data Compare
. Character compared correctly.
BIST Last Good
. Last Character of BIST sequence detected and valid.
Reserved.
BIST Last Bad
.
Last Character of BIST sequence detected invalid.
BIST Start
. Receive BIST is enabled on this channel, but character compares have not yet
commenced. This also indicates a PLL Out of Lock condition.
BIST Error
. While comparing characters, a mismatch was found in one or more of the character bits.
BIST Wait
. The receiver is comparing characters. but has not yet found the start of BIST character to
enable the LFSR.
110
111
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