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參數(shù)資料
| 型號(hào)： | CYW2338 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Dual Serial Input PLL with 2.5- and 1.1-GHz Prescalers |
| 中文描述： | 雙串行輸入鎖相環(huán)和1.1 - GHz的分頻器2.5 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大?。?/td> | 262K |
| 代理商： | CYW2338 |
PRELIMINARY
Dual Serial Input PLL with 2.5- and 1.1-GHz Prescalers
CYW2338
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
February 6, 2001, rev. **
12338\CYW2338
Features
Operating voltage 2.7V to 5.5V
Operating frequency to 2.5 GHz on PLL1 and 1.1 GHz
on PLL2 with prescaler ratios of 64/65 and 128/129
Lock detect feature
Power-down mode I
CC
< 1 μA typical at 3.0V
Serial data input accepts data clock rates as low as
1 kHz
Low power/voltage operation with low current standby
mode
On-chip reference oscillator
Available in a 20-pin TSSOP (Thin Shrink Small Outline
Package)
Available in a 24-pin CSP (Chip Scale Package)
Available in a 20-pin MLF
(Mirco Lead Frame Package)
Applications
The Cypress CYW2338 is a dual serial input PLL frequency
synthesizer designed for high performance dual conversion
TV, VCR, and Set-top tuner sections, as well as downstream
receivers for cable modems. The CYW2338 is also well suited
for high-volume, low-cost wireless communications applica-
tions. One 2.5-GHz and 1.1-GHz prescaler, each with pulse
swallow capability are included. The device operates from
2.7V and dissipates only 27 mW.
Dual PLL Block Diagram
Pin Configuration
Binary 7-Bit
Swallow Counter
Prescaler
64/65 or
128/129
Phase
Detector
Latch
PPLL1
Binary 11-Bit
Programmable Counter
20-Bit Latch
20-Bit Latch
Prescaler
64/65 or
128/129
Cntrl Shift
Reg.
Binary 4-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
Latch
PPLL2
Refere15-Bit
Refere15-Bit
Phase
Detector
Charge
Pump
fr fp
Monitor
Output
Selector
Charge
Pump
Power
Control
GND (17)
V
P
2 (19)
GND (14)
GND (4)
GND (7)
V
CC
1 (1)
V
CC
2 (20)
F
IN
1 (5)
F
IN
1# (6)
OSC_IN (8)
LE (13)
DATA (12)
CLOCK (11)
F
IN
2 (16)
F
IN
2# (15)
V
P
1 (2)
D
O
PLL1 (3)
F
O
/LD (10)
D
O
PLL2 (18)
Latch
Selector
fp1
fr1
fr2
fp2
V
CC
2
V
P
2
D
O
PLL2
GND
F
IN
2
F
IN
2#
GND
LE
DATA
CLOCK
20
19
18
17
16
15
14
13
12
11
V
CC
1
V
P
1
D
O
PLL1
GND
F
IN
1
F
IN
1#
GND
OSC_IN
OSC_OUT
F
O
/LD
1
2
3
4
5
6
7
8
9
10
(Top View)
1
2
3
4
5
15
14
13
12
6
7
8
9
1
2
1
1
1
1
11
DoPLL1
GND
Fin1
Fin1#
GND
GND
Fin2
Fin2#
GND
LE
O
G
F
C
D
V
V
V
V
D
(Top View)
4
5
6
7
19
18
17
16
1
1
1
2
2
2
15
3
DoPLL1
GND
Fin1
Fin1#
GND
GND
Fin2
Fin2#
GND
LE
G
F
C
V
V
V
2
1
NC
Vp1
8
9
OSC_IN
NC
14
13
DATA
NC
21
20
NC
DoPLL2
TSSOP
CSP
MLF
O
OSC_OUT (9)
O
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