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參數(shù)資料
| 型號： | CYW2338 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Dual Serial Input PLL with 2.5- and 1.1-GHz Prescalers |
| 中文描述： | 雙串行輸入鎖相環(huán)和1.1 - GHz的分頻器2.5 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 262K |
| 代理商： | CYW2338 |
CYW2338
PRELIMINARY
2
Pin Definitions
Pin Name
V
CC
1
Pin
No.
(TSSOP)
1
Pin
No.
(CSP)
24
Pin
No.
(MLF)
19
Pin
Type
P
Pin Description
Power Supply Connection for PLL1 and PLL2:
When pow-
er is removed from both the V
CC
1 and V
CC
2 pins, all latched
data is lost.
PLL1 Charge Pump Rail Voltage:
This voltage accommo-
dates VCO circuits with tuning voltages higher than the V
CC
of PLL1.
PLL1 Charge Pump Output:
The phase detector gain is
I
P
/2
π
. Sense polarity can be reversed by setting the FC bit in
software (via the Shift Register).
Input to PLL1 Prescaler:
Maximum frequency 2.5 GHz.
Complementary Input to PLL1 Prescaler:
A bypass capac-
itor should be placed as close as possible to this pin and must
be connected directly to the ground plane.
Oscillator Input:
This input has a V
CC
/2 threshold and CMOS
logic level sensitivity.
Oscillator Output
Lock Detect Pin of PLL1 Section:
This output is HIGH when
the loop is locked. It is multiplexed to the output of the pro-
grammable counters or reference dividers in the test program
mode. (Refer to
Table 3
for configuration.)
Data Clock Input:
One bit of data is loaded into the Shift
Register on the rising edge of this signal.
Serial Data Input
Load Enable:
On the rising edge of this signal, the data stored
in the Shift Register is latched into the reference counter and
configuration controls, PLL1 or PLL2 depending on the state
of the control bits.
Complementary Input to PLL2 Prescaler:
A bypass capac-
itor should be placed as close as possible to this pin and must
be connected directly to the ground plane.
Input to PLL2 Prescaler:
Maximum frequency 1.1 GHz.
PLL2 Charge Pump Output:
The phase detector gain is
I
P
/2
π
. Sense polarity can be reversed by setting the FC bit in
software (via the Shift Register).
PLL2 Charge Pump Rail Voltage:
This voltage accommo-
dates VCO circuits with tuning voltages higher than the V
CC
of PLL2.
Power Supply Connections for PLL1 and PLL2:
When
power is removed from both the V
CC
1 and V
CC
2 pins, all
latched data is lost.
Analog and Digital Ground Connections:
This pin must be
grounded.
No Connect.
V
P
1
2
2
20
P
D
O
PLL1
3
3
1
O
F
IN
1
F
IN
1#
5
6
5
6
3
4
I
I
OSC_IN
8
8
6
I
OSC_OUT
F
O
/LD
9
10
11
7
8
O
O
10
CLOCK
11
12
9
I
DATA
LE
12
13
14
15
10
11
I
I
F
IN
2#
15
17
13
I
F
IN
2
D
O
PLL2
16
18
18
20
14
16
I
O
V
P
2
19
22
17
P
V
CC
2
20
23
18
P
GND
4, 7, 14,
17
N/A
4, 7, 16,
19
1, 9, 13,
21
2, 5, 12,
15
N/A
G
N/C
N/C
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