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參數(shù)資料
| 型號： | CYV15G0404RB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock Quad HOTLink II Reclocking Deserializer(獨立時鐘，四路HOTLink II時鐘恢復串并轉(zhuǎn)換器) |
| 中文描述： | 獨立時鐘四的HOTLink第二時鐘重計解串器（獨立時鐘，四路的HOTLink第二時鐘恢復串并轉(zhuǎn)換器） |
| 文件頁數(shù)： | 8/26頁 |
| 文件大?。?/td> | 542K |
| 代理商： | CYV15G0404RB |
CYV15G0404RB
Document #: 38-02102 Rev. *B
Page 8 of 26
Pin Definitions
CYV15G0404RB Quad HOTLink II Deserializing Reclocker
Name
Receive Path Data and Status Signals
RXDA[9:0]
RXDB[9:0]
RXDC[9:0]
RXDD[9:0]
I/O Characteristics
Signal Description
LVTTL Output,
synchronous to the
RXCLK± output
Parallel Data Output
. RXDx[9:0] parallel data outputs change relative to the
receive interface clock. If RXCLKx± is a full-rate clock, the RXCLKx± clock outputs
are complementary clocks operating at the character rate. The RXDx[9:0] outputs
for the associated receive channels follow rising edge of RXCLKx+ or falling edge
of RXCLKx–. If RXCLKx± is a half-rate clock, the RXCLKx± clock outputs are
complementary clocks operating at half the character rate. The RXDx[9:0] outputs
for the associated receive channels follow both the falling and rising edges of the
associated RXCLKx± clock outputs.
When BIST is enabled on the receive channel, the BIST status is presented on
the RXDx[1:0] and BISTSTx outputs. See
Table 5
for each status reported by the
BIST state machine. Also, while BIST is enabled, the RXDx[9:2] outputs should
be ignored.
BIST Status Output.
When RXBISTx[1:0] = 10, BISTSTx (along with RXDx[1:0])
displays the status of the BIST reception. See
Table 5
for the BIST status reported
for each combination of BISTSTx and RXDx[1:0].
When RXBISTx[1:0]
≠
10, BISTSTx should be ignored.
Reclocker Powered Down Status Output.
REPDOx is asserted HIGH, when the
associated channel’s reclocker output logic is powered down. This occurs when
ROE2x and ROE1x are both disabled by setting ROE2x = 0 and ROE1x = 0.
BISTSTA
BISTSTB
BISTSTC
BISTSTD
LVTTL Output,
synchronous to the
RXCLKx ± output
REPDOA
REPDOB
REPDOC
REPDOD
Receive Path Clock Signals
TRGCLKA±
TRGCLKB±
TRGCLKC±
TRGCLKD±
Asynchronous to
reclocker output
channel
enable / disable
Differential LVPECL or
single-ended
LVTTL input clock
CDR PLL Training Clock
. TRGCLKx± clock inputs are used as the reference
source for the frequency detector (Range Controller) of the associated receive
PLL to reduce PLL acquisition time.
In the presence of valid serial data, the recovered clock output of the receive CDR
PLL (RXCLKx±) has no frequency or phase relationship with TRGCLKx±.
When driven by a single-ended LVCMOS or LVTTL clock source, connect the
clock source to either the true or complement TRGCLKx input, and leave the
alternate TRGCLKx input open (floating). When driven by an LVPECL clock
source, the clock must be a differential clock, using both inputs.
Receive Clock Output
. RXCLKx± is the receive interface clock used to control
timing of the RXDx[9:0] parallel outputs. These true and complement clocks are
used to control timing of data output transfers. These clocks are output continu-
ously at either the half-character rate (1/20
th
the serial bit-rate) or character rate
(1/10
th
the serial bit-rate) of the data being received, as selected by RXRATEx.
Reclocker Clock Output
. RECLKOx output clock is synthesized by the
associated reclocker output PLL and operates synchronous to the internal
recovered character clock. RECLKOx operates at either the same frequency as
RXCLKx± (RXRATEx = 0), or at twice the frequency of RXCLKx± (RXRATEx =
1).The reclocker clock outputs have no fixed phase relationship to RXCLKx±.
RXCLKA±
RXCLKB±
RXCLKC±
RXCLKD±
LVTTL Output Clock
RECLKOA
RECLKOB
RECLKOC
RECLKOD
LVTTL Output
Device Control Signals
RESET
LVTTL Input,
asynchronous,
internal pull-up
Asynchronous Device Reset
. RESET initializes all state machines, counters,
and configuration latches in the device to a known state. RESET must be asserted
LOW for a minimum pulse width. When the reset is removed, all state machines,
counters and configuration latches are at an initial state. See
Table 3
for the
initialize values of the device configuration latches.
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相關代理商/技術(shù)參數(shù) |
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| CYV15G0404RB_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Deserializing Reclocker |
| CYV15G0404RB-BGC | 功能描述:電信線路管理 IC 4x Indep Reclockers COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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