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參數(shù)資料
| 型號： | CYV15G0404RB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock Quad HOTLink II Reclocking Deserializer(獨(dú)立時(shí)鐘，四路HOTLink II時(shí)鐘恢復(fù)串并轉(zhuǎn)換器) |
| 中文描述： | 獨(dú)立時(shí)鐘四的HOTLink第二時(shí)鐘重計(jì)解串器（獨(dú)立時(shí)鐘，四路的HOTLink第二時(shí)鐘恢復(fù)串并轉(zhuǎn)換器） |
| 文件頁數(shù)： | 15/26頁 |
| 文件大小： | 542K |
| 代理商： | CYV15G0404RB |
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CYV15G0404RB
Document #: 38-02102 Rev. *B
Page 15 of 26
Device Configuration Strategy
The following is a series of ordered events needed to load the
configuration latches on a per channel basis:
1. Pulse RESET Low after device power-up. This operation
resets all four channels.
2. Set the static latch banks for the target channel. May be
performed using a global operation, if the application
permits it. [Optional step if the default settings match the
desired configuration.]
3. Set the dynamic bank of latches for the target channel.
Enable the Receive PLLs and set each channel for SMPTE
data reception (RXBISTx[1:0] = 01) or BIST data reception
(RXBISTx[1:0] = 10). May be performed using a global
operation, if the application permits it. [Required step.]
ROE1A
ROE1B
ROE1C
ROE1D
Reclocker Primary Differential Serial Data Output Driver Enable
. The initialization value of the ROE1x
latch = 0. ROE1x selects if the ROUT1± primary differential output drivers are enabled or disabled. When
ROE1x = 1, the associated serial data output driver is enabled allowing data to be transmitted from the
transmit shifter. When ROE1x = 0, the associated serial data output driver is disabled. When a driver is
disabled via the configuration interface, it is internally powered down to reduce device power. If both serial
drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered
down. A device reset (RESET sampled LOW) disables all output drivers.
Global Enable
. The initialization value of the GLENx latch = 1. The GLENx is used to reconfigure several
channels simultaneously in applications where several channels may have the same configuration. When
GLENx = 1 for a given address, that address is allowed to participate in a global configuration. When
GLENx = 0 for a given address, that address is disabled from participating in a global configuration.
Force Global Enable
. The initialization value of the FGLENx latch is NA. The FGLENx latch forces a
GLobal ENable no matter what the setting is on the GLENx latch. If FGLENx = 1 for the associated Global
channel, FGLEN forces the global update of the target latch banks.
GLEN[11..0]
FGLEN[2..0]
Table 3. Device Configuration and Control Latch Descriptions
(continued)
Name
Signal Description
Table 4. Device Control Latch Configuration Table
ADDR
Channel Type
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Reset
Value
0
(0000b)
A
S
1
0
X
X
0
0
RXRATEA
GLEN0
10111111
1
(0001b)
A
S
SDASEL2A[1]
SDASEL2A[0]
SDASEL1A[1]
SDASEL1A[0]
X
X
TRGRATEA
GLEN1
10101101
2
(0010b)
A
D
RXBISTA[1]
RXPLLPDA
RXBISTA[0]
X
ROE2A
ROE1A
X
GLEN2
10110011
3
(0011b)
B
S
1
0
X
X
0
0
RXRATEB
GLEN3
10111111
4
(0100b)
B
S
SDASEL2B[1]
SDASEL2B[0]
SDASEL1B[1]
SDASEL1B[0]
X
X
TRGRATEB
GLEN4
10101101
5
(0101b)
B
D
RXBISTB[1]
RXPLLPDB
RXBISTB[0]
X
ROE2B
ROE1B
X
GLEN5
10110011
6
(0110b)
C
S
1
0
X
X
0
0
RXRATEC
GLEN6
10111111
7
(0111b)
C
S
SDASEL2C[1]
SDASEL2C[0]
SDASEL1C[1]
SDASEL1C[0]
X
X
TRGRATEC
GLEN7
10101101
8
(1000b)
C
D
RXBISTC[1]
RXPLLPDC
RXBISTC[0]
X
ROE2C
ROE1C
X
GLEN8
10110011
9
(1001b)
D
S
1
0
X
X
0
0
RXRATED
GLEN9
10111111
10
(1010b)
D
S
SDASEL2D[1]
SDASEL2D[0]
SDASEL1D[1]
SDASEL1D[0]
X
X
TRGRATED
GLEN10
10101101
11
(1011b)
D
D
RXBISTD[1]
RXPLLPDD
RXBISTD[0]
X
ROE2D
ROE1D
X
GLEN11
10110011
12
(1100b)
GLOBAL
S
1
0
X
X
0
0
RXRATEGL
FGLEN0
N/A
13
(1101b)
GLOBAL
S
SDASEL2GL[1] SDASEL2GL[0] SDASEL1GL[1] SDASEL1GL[0]
X
X
TRGRATEGL
FGLEN1
N/A
14
(1110b)
GLOBAL
D
RXBISTGL[1]
RXPLLPDGL
RXBISTGL[0]
X
ROE2GL
ROE1GL
X
FGLEN2
N/A
15
(1111b)
MASK
D
D7
D6
D5
D4
D3
D2
D1
D0
11111111
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