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參數(shù)資料
| 型號： | CYV15G0404DXB-BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Transceiver with Reclocker |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, TBGA-256 |
| 文件頁數(shù)： | 8/43頁 |
| 文件大小： | 814K |
| 代理商： | CYV15G0404DXB-BGC |
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PRELIMINARY
CYV15G0404DXB
Document #: 38-02097 Rev. **
Page 8 of 43
Pin Definitions
CYV15G0404DXB Quad HOTLink II Transceiver
Name
Transmit Path Data and Status Signals
TXDA[7:0]
TXDB[7:0]
TXDC[7:0]
TXDD[7:0]
I/O Characteristics
Signal Description
LVTTL Input,
synchronous,
sampled by the
associated
TXCLKx
↑
or
REFCLKx
↑
[2]
LVTTL Input,
synchronous,
sampled by the
associated
TXCLKx
↑
or
REFCLKx
↑
[2]
Transmit Data Inputs
. TXDx[7:0] data inputs are captured on the rising edge of
the transmit interface clock. The transmit interface clock is selected by the
TXCLKSELx latch via the device configuration interface, and passed to the
encoder or Transmit Shifter. When the Encoder is enabled, TXDx[7:0] specifies
the specific data or command character sent.
TXCTA[1:0]
TXCTB[1:0]
TXCTC[1:0]
TXCTD[1:0]
Transmit Control
. TXCTx[1:0] inputs are captured on the rising edge of the
transmit interface clock. The transmit interface clock is selected by the
TXCLKSELx latch via the device configuration interface, and passed to the
Encoder or Transmit Shifter. The TXCTA[1:0] inputs identify how the associated
TXDx[7:0] characters are interpreted. When the Encoder is bypassed, these
inputs are interpreted as data bits. When the Encoder is enabled, these inputs
determine if the TXDx[7:0] character is encoded as Data, a Special Character
code, or replaced with other Special Character codes. See
Table 3
for details.
Transmit Path Error
. TXERRx is asserted HIGH to indicate detection of a
transmit Phase-Align Buffer underflow or overflow. If an underflow or overflow
condition is detected, TXERRx, for the channel in error, is asserted HIGH and
remains asserted until either a Word Sync Sequence is transmitted on that
channel, or the transmit Phase-Align Buffer is re-centered with the PABRSTx latch
via the device configuration interface. When TXBISTx = 0, the BIST progress is
presented on the associated TXERRx output. The TXERRx signal pulses HIGH
for one transmit-character clock period to indicate a pass through the BIST
sequence once every 511 or 527 (depending on RXCKSELx) character times. If
RXCKSELx = 1, a one character pulse occurs every 527 character times. If
RXCKSELx = 0, a one character pulse occurs every 511 character times.
TXERRx is also asserted HIGH, when any of the following conditions is true:
The TXPLL for the associated channel is powered down. This occurs when
OE2x and OE1x for a given channel are simultaneous disabled by setting OE2x
= 0 and OE1x = 0.
The absence of the REFCLKx± signal.
TXERRA
TXERRB
TXERRC
TXERRD
LVTTL Output,
synchronous to
REFCLKx
↑
[3]
,
synchronous to
RXCLKx when
selected as
REFCLKx,
asynchronous to
transmit channel
enable / disable,
asynchronous to loss
or return of
REFCLKx±
Transmit Path Clock Signals
REFCLKA±
REFCLKB±
REFCLKC±
REFCLKD±
Differential LVPECL
or single-ended
LVTTL input clock
Reference Clock
. REFCLKx± clock inputs are used as the timing references for
the transmit and receive PLLs. These input clocks may also be selected to clock
the transmit and receive parallel interfaces. When driven by a single-ended
LVCMOS or LVTTL clock source, connect the clock source to either the true or
complement REFCLKx input, and leave the alternate REFCLKx input open
(floating). When driven by an LVPECL clock source, the clock must be a differ-
ential clock, using both inputs.
Transmit Path Input Clock
. When configuration latch TXCKSELx = 0, the
associated TXCLKx input is selected as the character-rate input clock for the
TXDx[7:0] and TXCTx[1:0] inputs. In this mode, the TXCLKx input must be
frequency-coherent to its associated TXCLKOx output clock, but may be offset in
phase by any amount. Once initialized, TXCLKx is allowed to drift in phase as
much as ±180 degrees. If the input phase of TXCLKx drifts beyond the handling
capacity of the Phase Align Buffer, TXERRx is asserted to indicate the loss of data,
and remains asserted until the Phase Align Buffer is initialized. The phase of the
TXCLKx input clock relative to its associated REFCLKx± is initialized when the
configuration latch PABRSTx is written as 0. When the associated TXERRx is
deasserted, the Phase Align Buffer is initialized and input characters are correctly
captured.
TXCLKA
TXCLKB
TXCLKC
TXCLKD
LVTTL Clock Input,
internal pull-down
Notes:
2.
3.
When REFCLKx± is configured for half-rate operation, these inputs are sampled relative to both the rising and falling edges of the associated REFCLKx±.
When REFCLKx± is configured for half-rate operation, these outputs are presented relative to both the rising and falling edges of the associated REFCLKx±.
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| CYV15G0404DXB-BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Transceiver with Reclocker |
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