參數(shù)資料
型號(hào)： CYV15G0404DXB-BGC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Independent Clock Quad HOTLink II⑩ Transceiver with Reclocker
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, 1.57 MM HEIGHT, TBGA-256
文件頁(yè)數(shù)： 21/43頁(yè)
文件大?。?/td> 814K
代理商： CYV15G0404DXB-BGC
PRELIMINARY
CYV15G0404DXB
Document #: 38-02097 Rev. **
Page 21 of 43
RXRATEA
RXRATEB
RXRATEC
RXRATED
Receive Clock Rate Select
. The initialization value of the RXRATEx latch = 1. RXRATEx is used to
select the rate of the RXCLKx± clock output.
When RXRATEx = 1 and RXCKSELx = 0, the RXCLKx± clock outputs are complementary clocks that
follow the recovered clock operating at half the character rate. Data for the associated receive channels
should be latched alternately on the rising edge of RXCLKx+ and RXCLKx–.
When RXRATEx = 0 and RXCKSELx = 0, the RXCLKx± clock outputs are complementary clocks that
follow the recovered clock operating at the character rate. Data for the associated receive channels
should be latched on the rising edge of RXCLKx+ or falling edge of RXCLKx–.
When RXRATEx = 1 with RXCKSELx = 1 and REFCLKx± is a full-rate clock, the RXCLKx± clock outputs
are complementary clocks that follow the reference clock operating at half the character rate. Data for
the associated receive channels should be latched alternately on the rising edge of RXCLKx+ and
RXCLKx–.
When RXRATEx = 0 with RXCKSELx = 1 and REFCLKx± is a full-rate clock, the RXCLKx± clock outputs
are complementary clocks that follow the reference clock operating at the character rate. Data for the
associated receive channels should be latched on the rising edge of RXCLKx+ or falling edge of
RXCLKx–.
When RXCKSELx = 1 and REFCLKx± is a half-rate clock, the value of RXRATEx is not interpreted and
the RXCLKx± clock outputs are complementary clocks that follow the reference clock operating at half
the character rate. Data for the associated receive channels should be latched alternately on the rising
edge of RXCLKx+ and RXCLKx–.
Primary Serial Data Input Signal Detector Amplitude Select
. The initialization value of the
SDASEL1x[1:0] latch = 10. SDASEL1x[1:0] selects the trip point for the detection of a valid signal for the
INx1± Primary Differential Serial Data Inputs.
When SDASEL1x[1:0] = 00, the Analog Signal Detector is disabled.
When SDASEL1x[1:0] = 01, the typical p-p differential voltage threshold level is 140mV.
When SDASEL1x[1:0] = 10, the typical p-p differential voltage threshold level is 280mV.
When SDASEL1x[1:0] = 11, the typical p-p differential voltage threshold level is 420mV.
Secondary Serial Data Input Signal Detector Amplitude Select
. The initialization value of the
SDASEL2x[1:0] latch = 10. SDASEL2x[1:0] selects the trip point for the detection of a valid signal for the
INx2± Secondary Differential Serial Data Inputs.
When SDASEL2x[1:0] = 00, the Analog Signal Detector is disabled
When SDASEL2x[1:0] = 01, the typical p-p differential voltage threshold level is 140mV.
When SDASEL2x[1:0] = 10, the typical p-p differential voltage threshold level is 280mV.
When SDASEL2x[1:0] = 11, the typical p-p differential voltage threshold level is 420mV.
Transmit Encoder Bypassed
. The initialization value of the ENCBYPx latch = 1. ENCBYPx selects if
the Transmit Encoder is enabled or bypassed. When ENCBYPx = 1, the Transmit encoder is enabled.
When ENCBYPx = 0, the Transmit Encoder is bypassed and raw 10-bit characters are transmitted.
SDASEL1A[1:0]
SDASEL1B[1:0]
SDASEL1C[1:0]
SDASEL1D[1:0]
SDASEL2A[1:0]
SDASEL2B[1:0]
SDASEL2C[1:0]
SDASEL2D[1:0]
ENCBYPA
ENCBYPB
ENCBYPC
ENCBYPD
TXCKSELA
TXCKSELB
TXCKSELC
TXCKSELD
Transmit Clock Select
. The initialization value of the TXCKSELx latch = 1. TXCKSELx selects the clock
source used to write data into the Transmit Input Register. When TXCKSELx = 1, the associated input
register, TXDx[7:0] and TXCTx[1:0], is clocked by REFCLKx
↑.
In this mode, the phase alignment buffer
in the transmit path is bypassed. When TXCKSELx = 0, the associated TXCLKx
↑
is used to clock in the
input registers, TXDx[7:0] and TXCTx[1:0].
Transmit PLL Clock Rate Select
. The initialization value of the TXRATEx latch = 0. TXRATEx is used
to select the clock multiplier for the Transmit PLL. When TXRATEx = 0, each transmit PLL multiples the
associated REFCLKx± input by 10 to generate the serial bit-rate clock. When TXRATEx = 0, the
TXCLKOx output clocks are full-rate clocks and follow the frequency and duty cycle of the associated
REFCLKx± input. When TXRATEx = 1, each Transmit PLL multiplies the associated REFCLKx± input
by 20 to generate the serial bit-rate clock. When TXRATEx = 1, the TXCLKOx output clocks are twice
the frequency rate of the REFCLKx± input. When TXCLKSELx = 1 and TXRATEx = 1, the Transmit Data
Inputs are captured using both the rising and falling edges of REFCLKx. TXRATEx = 1 and SPDSELx
is LOW, is an invalid state and this combination is reserved.
Reframe Enable
. The initialization value of the RFENx latch = 1. RFENx selects if the receiver framer
is enabled or disabled. When RFENx = 1, the associated channel’s framer is enabled to frame per the
presently enabled framing mode and selected framing character. When RFENx = 0, the associated
channel’s framer is disabled, and no received bits alters the frame offset.
TXRATEA
TXRATEB
TXRATEC
TXRATED
RFENA
RFENB
RFENC
RFEND
Table 9. Device Configuration and Control Latch Descriptions
(continued)
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