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參數(shù)資料
| 型號： | CYV15G0404DXB-BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Transceiver with Reclocker |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, TBGA-256 |
| 文件頁數(shù)： | 18/43頁 |
| 文件大?。?/td> | 814K |
| 代理商： | CYV15G0404DXB-BGC |
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PRELIMINARY
CYV15G0404DXB
Document #: 38-02097 Rev. **
Page 18 of 43
The receive BIST state machine requires the characters to be
correctly framed for it to detect the BIST sequence. If the Low
Latency Framer is enabled, the Framer misaligns to an aliased
SYNC character within the BIST sequence. If the Alternate
Multi-Byte Framer is enabled and the Receiver outputs are
clocked relative to a recovered clock, it is generally necessary
to frame the receiver before BIST is enabled. If the receive
outputs are clocked relative to REFCLKx±, the transmitter
precedes every 511 character BIST sequence with a 16
character-character Word Sync Sequence.
A device reset (RESET sampled LOW) presets the BIST
Enable Latches to disable BIST on all channels.
Receive Elasticity Buffer
Each receive channel contains an Elasticity Buffer that is
designed to support multiple clocking modes. These buffers
allow data to be read using a clock that is asynchronous in both
frequency and phase from the Elasticity Buffer write clock, or
to be read using a clock that is frequency coherent but with
uncontrolled phase relative to the Elasticity Buffer write clock.
If the chip is configured for operation with a recovered clock,
the Elasticity Buffer is bypassed.
Each Elasticity Buffer is 10 characters deep, and supports and
an 11 bit wide data path. It is capable of supporting a decoded
character and three status bits for each character present in
the buffer. The write clock for these buffers is always the
recovered clock for the associated read channel.
Receive Modes
When the receive channel is clocked by REFCLKx±, the
RXCLKx± outputs present a buffered or divided (depending on
RXRATEx) and delayed form of REFCLKx±. In this mode, the
receive Elasticity Buffers are enabled. For REFCLKx±
clocking, the Elasticity Buffers must be able to insert K28.5
characters and delete framing characters as appropriate.
The insertion of a K28.5 or deletion of a framing character can
occur at any time on any channel, however, the actual timing
of these insertions and deletions is controlled in part by how
the transmitter sends its data. Insertion of a K28.5 character
can only occur when the receiver has a framing character in
the Elasticity Buffer. Likewise, to delete a framing character,
one must also be in the Elasticity Buffer. To prevent a buffer
overflow or underflow on a receive channel, a minimum
density of framing characters must be present in the received
data streams.
When the receive channel Output Register is clocked by a
recovered clock, no characters are added or deleted and the
receiver Elasticity Buffer is bypassed.
Power Control
The CYV15G0404DXB supports user control of the powered
up or down state of each transmit and receive channel. The
receive channels are controlled by the RXPLLPDx latch via the
device configuration interface. When RXPLLPDx = 0, the
associated PLL and analog circuitry of the channel is disabled.
The transmit channels are controlled by the OE1x and the
OE2x latches via the device configuration interface. When a
driver is disabled via the configuration interface, it is internally
powered down to reduce device power. If both serial drivers
for a channel are in this disabled state, the associated internal
logic for that channel is also powered down.
Device Reset State
When the CYV15G0404DXB is reset by assertion of RESET,
all state machines, counters, and configuration latches in the
device are initialized to a reset state, and the Elasticity Buffer
pointers are set to a nominal offset. See
Table 9
for the
initialize values of the configuration latches.
Following a device reset, it is necessary to enable the transmit
and receive channels used for normal operation. This can be
done by sequencing the appropriate values on the device
configuration interface.
[5]
Output Bus
Each receive channel presents an 11-signal output bus
consisting of
an 8-bit data bus
a 3-bit status bus.
The signals present on this output bus are modified by the
present operating mode of the CYV15G0404DXB as selected
by the DECBYPx and DECMODEx configuration latch. This
mapping is shown in
Table 7
.
Table 7. Output Register Bit Assignments
When the 10B/8B decoder is bypassed, the framed 10-bit
value is presented to the associated Output Register, along
with a status output signal indicating if the character in the
Output Register is one of the selected framing characters. The
bit usage and mapping of the external signals to the raw 10B
transmission character is shown in
Table 8
.
The COMDETx status output operates the same regardless of
the bit combination selected for character framing by the
FRAMCHARx latch. COMDETx is HIGH when the character in
the output register contains the selected framing character at
the proper character boundary, and LOW for all other bit
combinations.
When the low-latency framer and half-rate receive port
clocking are also enabled, the framer stretches the recovered
clock to the nearest 20-bit boundary such that the rising edge
of RXCLKx+ occurs when COMDETx is present on the
associated output bus.
When the Cypress or Alternate Mode Framer is enabled and
half-rate receive port clocking is also enabled, the output clock
is not modified when framing is detected, but a single pipeline
Signal Name
RXSTx[2] (LSB)
RXSTx[1]
RXSTx[0]
RXDx[0]
RXDx[1]
RXDx[2]
RXDx[3]
RXDx[4]
RXDx[5]
RXDx[6]
RXDx[7] (MSB)
BYPASS ACTIVE
(DECBYPx = 0 and
DECMODEx = 1)
COMDETx
DOUTx[0]
DOUTx[1]
DOUTx[2]
DOUTx[3]
DOUTx[4]
DOUTx[5]
DOUTx[6]
DOUTx[7]
DOUTx[8]
DOUTx[9]
DECODER
(DECBYP = 1)
RXSTx[2]
RXSTx[1]
RXSTx[0]
RXDx[0]
RXDx[1]
RXDx[2]
RXDx[3]
RXDx[4]
RXDx[5]
RXDx[6]
RXDx[7]
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| CYV15G0404DXB-BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Transceiver with Reclocker |
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