參數(shù)資料
型號： CYV15G0404DXB-BGC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Independent Clock Quad HOTLink II⑩ Transceiver with Reclocker
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, 1.57 MM HEIGHT, TBGA-256
文件頁數(shù)： 33/43頁
文件大?。?/td> 814K
代理商： CYV15G0404DXB-BGC
PRELIMINARY
CYV15G0404DXB
Document #: 38-02097 Rev. **
Page 33 of 43
Table 12. Package Coordinate Signal Allocation
Ball
ID
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C01
C02
C03
Signal Name
INC1–
OUTC1–
INC2–
OUTC2–
VCC
IND1–
OUTD1–
GND
IND2–
OUTD2–
INA1–
OUTA1–
GND
INA2–
OUTA2–
VCC
INB1–
OUTB1–
INB2–
OUTB2–
INC1+
OUTC1+
INC2+
OUTC2+
VCC
IND1+
OUTD1+
GND
IND2+
OUTD2+
INA1+
OUTA1+
GND
INA2+
OUTA2+
VCC
INB1+
OUTB1+
INB2+
OUTB2+
TDI
TMS
INSELC
Signal Type
CML IN
CML OUT
CML IN
CML OUT
POWER
CML IN
CML OUT
GROUND
CML IN
CML OUT
CML IN
CML OUT
GROUND
CML IN
CML OUT
POWER
CML IN
CML OUT
CML IN
CML OUT
CML IN
CML OUT
CML IN
CML OUT
POWER
CML IN
CML OUT
GROUND
CML IN
CML OUT
CML IN
CML OUT
GROUND
CML IN
CML OUT
POWER
CML IN
CML OUT
CML IN
CML OUT
LVTTL IN PU
LVTTL IN PU
LVTTL IN
Ball
ID
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
E01
E02
E03
E04
E17
E18
E19
E20
F01
Signal Name
ULCC
GND
DATA[7]
DATA[5]
DATA[3]
DATA[1]
GND
RCLKENB
SPDSELD
VCC
LDTDEN
TRST
LPEND
TDO
TCLK
RESET
INSELD
INSELA
VCC
ULCA
SPDSELC
GND
DATA[6]
DATA[4]
DATA[2]
DATA[0]
GND
LPENB
ULCB
VCC
LPENA
VCC
SCANEN2
TMEN3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RXDC[6]
Signal Type
LVTTL IN PU
GROUND
LVTTL IN PU
LVTTL IN PU
LVTTL IN PU
LVTTL IN PU
GROUND
LVTTL IN PD
3-LEVEL SEL
POWER
LVTTL IN PU
LVTTL IN PU
LVTTL IN PD
LVTTL 3-S OUT
LVTTL IN PD
LVTTL IN PU
LVTTL IN
LVTTL IN
POWER
LVTTL IN PU
3-LEVEL SEL
GROUND
LVTTL IN PU
LVTTL IN PU
LVTTL IN PU
LVTTL IN PU
GROUND
LVTTL IN PD
LVTTL IN PU
POWER
LVTTL IN PD
POWER
LVTTL IN PD
LVTTL IN PD
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
LVTTL OUT
Ball
ID
F17
F18
F19
F20
G01
G02
G03
G04
G17
G18
G19
G20
H01
H02
H03
H04
H17
H18
H19
H20
J01
J02
J03
J04
J17
J18
J19
J20
K01
K02
K03
K04
K17
K18
K19
K20
L01
L02
L03
L04
L17
L18
L19
Signal Name
RCLKENA
RXSTB[1]
TXCLKOB
RXSTB[0]
TXDC[7]
WREN
TXDC[4]
TXDC[1]
SPDSELB
LPENC
SPDSELA
RXDB[1]
GND
GND
GND
GND
GND
GND
GND
GND
TXCTC[1]
TXDC[5]
TXDC[2]
TXDC[3]
RXSTB[2]
RXDB[0]
RXDB[5]
RXDB[2]
RXDC[2]
REFCLKC–
TXCTC[0]
TXCLKC
RXDB[3]
RXDB[4]
RXDB[7]
LFIB
RXDC[3]
REFCLKC+
LFIC
TXDC[6]
RXDB[6]
RXCLKB+
RXCLKB–
Signal Type
LVTTL IN PD
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL IN
LVTTL IN PU
LVTTL IN
LVTTL IN
3-LEVEL SEL
LVTTL IN PD
3-LEVEL SEL
LVTTL OUT
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
PECL IN
LVTTL IN
LVTTL IN PD
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
PECL IN
LVTTL OUT
LVTTL IN
LVTTL OUT
LVTTL OUT
LVTTL OUT
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CYV15G0404DXB-BGI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Transceiver with Reclocker
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