
PRELIMINARY
CYV15G0404DXB
Document #: 38-02097 Rev. **
Page 2 of 43
The CYV15G0404DXB satisfies the SMPTE-259M and
SMPTE-292M compliance as per SMPTE EG34-1999 Patho-
logical Test Requirements.
As a second-generation HOTLink device, the CYV15G0404DXB
extends the HOTLink family with enhanced levels of integration
and faster data rates, while maintaining serial-link compatibility
(data, command, and BIST) with other HOTLink devices. The
transmit (TX) section of the CYV15G0404DXB Quad HOTLink II
consists of four independent byte-wide channels. Each channel
can accept either 8-bit data characters or preencoded 10-bit
transmission characters. Data characters may be passed from
the Transmit Input Register to an integrated 8B/10B Encoder
to improve their serial transmission characteristics. These
encoded characters are then serialized and output from dual
Positive ECL (PECL) compatible differential transmission-line
drivers at a bit-rate of either 10- or 20-times the input reference
clock for that channel.
The receive (RX) section of the CYV15G0404DXB Quad
HOTLink II consists of four independent byte-wide channels.
Each channel accepts a serial bit-stream from one of two
PECL-compatible differential line receivers, and using a
completely integrated Clock and Data Recovery PLL, recovers
the timing information necessary for data reconstruction. Each
recovered bit-stream is deserialized and framed into
CYV15G0404DXB Transceiver Logic Block Diagram
characters, 8B/10B decoded, and checked for transmission
errors. Recovered decoded characters are then written to an
internal Elasticity Buffer, and presented to the destination host
system.
The integrated 8B/10B encoder/decoder may be bypassed for
systems that present externally encoded or scrambled data at
the parallel interface.
The parallel I/O interface may be configured for numerous
forms of clocking to provide the highest flexibility in system
architecture. In addition to clocking the transmit path with a
local reference clock, the receive interface may also be
configured to present data relative to a recovered clock or to a
local reference clock.
Each transmit and receive channel contains an independent
BIST pattern generator and checker. This BIST hardware
allows at-speed testing of the high-speed serial data paths in
each transmit and receive section, and across the intercon-
necting links.
The CYV15G0404DXB is ideal for port applications where
different data rates and serial interface standards are
necessary for each channel. Some applications include multi-
format routers and switchers.
x10
Serializer
Phase
Align
Buffer
Encoder
8B/10B
Decoder
8B/10B
x11
Framer
Deserializer
TX
RX
x10
Serializer
Encoder
8B/10B
Decoder
8B/10B
x11
Framer
Deserializer
TX
RX
x10
Serializer
Encoder
8B/10B
Decoder
8B/10B
x11
Framer
Deserializer
TX
RX
x10
Serializer
Encoder
8B/10B
Decoder
8B/10B
x11
Framer
Deserializer
TX
RX
T
R
T
R
T
R
T
R
O
A
±
O
±
I
±
I
±
O
±
O
±
I
±
I
±
O
±
O
±
I
±
I
±
O
±
O
±
I
±
I
±
Phase
Align
Buffer
Phase
Align
Buffer
Phase
Align
Buffer
Elasticity
Buffer
Elasticity
Buffer
Elasticity
Buffer
Elasticity
Buffer
T
R
T
R
T
R
T
R
R
R
R
R